similar to: Questions on Maxwell/Pascal Texture Instructions Modes

Generated with envysched. Tested by running rendercheck from piglit, running mplayer -vo xv, and staring at gnome-shell. Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com> --- src/shader/exac8nv110.fp | 11 ++++---- src/shader/exac8nv110.fpc | 22 ++++++++-------- src/shader/exacanv110.fp | 11 ++++---- src/shader/exacanv110.fpc | 22 ++++++++-------- src/shader/exacmnv110.fp | 10

This is parallel to the pre-SM50 change which does this. Adjusts the shuffles / quadops to make the values correct relative to lane 0, and then splat the results to all lanes for the final move into the target register. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Entirely untested beyond compilation. Should check bin/tex-miplevel-selection textureGrad Cube

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nouveau_copy.c | 2 ++ src/nvc0_accel.c | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index c139de6..7118a7a 100644 --- a/src/nouveau_copy.c +++ b/src/nouveau_copy.c @@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen) int engine; Bool

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Untested. src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 3 +++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 14 insertions(+) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index 7118a7a..7fbcc87 100644 --- a/src/nouveau_copy.c

So I have been going on over the documentation trying to figure out the exact layout of Pitch Linear Textures and find some missing values. First Question: What's the correct layout of pitch linear textures in memory? Is padding of the pitch added at start or at the end? Do they have some kind of header? Currently I see them as a normal texture matrix with just pitch at the end of each row

0xc0b5 is not in rnndb, I guess it should be GP100_COPY, right? Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nouveau_copy.c | 2 ++ > src/nvc0_accel.c | 10 +++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- v1 -> v2: add 0x130 as a valid chip type early on in detection src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 4 ++++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 15 insertions(+) diff --git a/src/nouveau_copy.c

So we are currently doing tests and complying with them in our Emulator. Currently the conditional rendering test does not pass (no wonder we not even implement it). I've been looking at the current documentation https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml#L796 So far I don't understand how the cond address is used and to what it's compared.

Hi People! I have following concern consisting of some steps to do in R: I have an ascii file (table) consisting of many columns and rows. 1. I would like to order all values of the columns one under each other. It will begin with column 1, then column 2 under column 1, column 3 under column 2 etc. until at the end there is only 1 column. How do I do it? 2. Second problem is to make a

On Mon, Feb 15, 2016 at 4:40 PM, Ben Skeggs <skeggsb at gmail.com> wrote: > On 02/16/2016 03:47 AM, Ilia Mirkin wrote: >> Can you push this to a repo somewhere? I want to see what the final >> version looks like after all your changes, but it's hard to see that >> with these patches. > https://github.com/skeggsb/Mesa/commits/master Thanks. I looked over this

From: Ben Skeggs <bskeggs at redhat.com> Adds support for the new TIC layout that's present on Maxwell GPUs, heavily based on the code for the existing layout. This code is required for GM20x support. While GM10x supports the older layout still, this commit switches it to use the updated version instead. Piglit testing shows zero regressions on GM107. Signed-off-by: Ben Skeggs

On 02/16/2016 03:47 AM, Ilia Mirkin wrote: > Can you push this to a repo somewhere? I want to see what the final > version looks like after all your changes, but it's hard to see that > with these patches. https://github.com/skeggsb/Mesa/commits/master > > On Mon, Feb 15, 2016 at 12:38 AM, Ben Skeggs <skeggsb at gmail.com> wrote: >> From: Ben Skeggs <bskeggs at

Can you push this to a repo somewhere? I want to see what the final version looks like after all your changes, but it's hard to see that with these patches. On Mon, Feb 15, 2016 at 12:38 AM, Ben Skeggs <skeggsb at gmail.com> wrote: > From: Ben Skeggs <bskeggs at redhat.com> > > Adds support for the new TIC layout that's present on Maxwell GPUs, > heavily based on

Hi, By using virtio-win-0.1.109.iso , it looks like vport0p devices are not configured (on a Windows 2008 R2 guest) due to no suitable driver found ( below setupapi.dev.log): [Boot Session: 2015/09/16 17:29:32.375] >>> [Device Install (Hardware initiated) - {6fde7547-1b65-48ae-b628-80be62016026}\vioserialport\4&7e8053e&1&03] >>> Section start 2015/09/16

I believe I've addressed all the feedback from the first time around, and also made fixes necessary for GM20x based on testing results. I believe now it should actually work for all GM10x and GM20x. Further, GP10x should be very easy to add, but without someone to actually test I didn't want to claim support for it. Ilia Mirkin (7): exa: add GM10x acceleration support hwdefs: update

v4: Updated the wait dependancy bars based on tex component masks. This patch adds proper delays to maxwell exa shaders. Tested with rendercheck -f a8r8g8b8. I am still wondering whether the rd's are required. We could still wait on the write bars instead. eg. see "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp Trello:

Removed explicit depar instructions as they're not used by the blob anymore. Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 5 ++--- src/shader/exac8nv110.fpc | 10 ++++------ src/shader/exacanv110.fp | 5 ++--- src/shader/exacanv110.fpc | 10 ++++------ src/shader/exacmnv110.fp | 5 ++--- src/shader/exacmnv110.fpc | 10 ++++------

Sorry for the late response, been busy with some personal stuff + work... On Tue, Jun 13, 2017 at 6:52 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Mon, Jun 12, 2017 at 5:46 PM, Samuel Pitoiset > <samuel.pitoiset at gmail.com> wrote: > > > > > > On 06/10/2017 09:14 AM, Aaryaman Vasishta wrote: > >> > >> See the 'wt' on the

This patch adds proper delays to maxwell exa shaders. rendercheck tests seem consistent with/without this patch. I haven't extensively tested them though. Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 10 +++++----- src/shader/exac8nv110.fpc | 18

v2: Add missing delays This patch adds proper delays to maxwell exa shaders. rendercheck tests seem consistent with/without this patch. I haven't extensively tested them though. Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 10 +++++-----