similar to: State of Video Decoding for Maxwell cards

Well, you are most likely using the CPU for decoding here. Currently nobody is working on that, because this is quite a big and challenging project. We have an open project idea regarding this for EVoC and GSoC though: "Maxwell Accelerated Video Decoding" https://www.x.org/wiki/SummerOfCodeIdeas/ On Thu, Nov 30, 2017 at 1:18 PM, Christoph Böhmwalder <christoph at boehmwalder.at>

The kbuild test bot complained about a new coccinelle warning nearby, which sparked a discussion about the assignment to 'memory' inside of the conditional expression. See Link below for the original post. Fix the assignment to silence the coccinelle warning and also make the code look a little nicer. Link: https://lists.freedesktop.org/archives/nouveau/2017-November/029242.html

Hi everybody, currently on the Xorg Wiki page [1] there are only three projects ideas, two being quite similiar: 1. Instruction scheduling 2. Maxwell Video Accel Decoding 3. Kepler Video Accel Encoding and also the reference to our Trello board. Because I don't expect any student interested in a GSoC/EVoC project to read our wiki or trello, I am sure to attract more students, we should give

On Mon, Feb 15, 2016 at 4:40 PM, Ben Skeggs <skeggsb at gmail.com> wrote: > On 02/16/2016 03:47 AM, Ilia Mirkin wrote: >> Can you push this to a repo somewhere? I want to see what the final >> version looks like after all your changes, but it's hard to see that >> with these patches. > https://github.com/skeggsb/Mesa/commits/master Thanks. I looked over this

Hello, The method we previously used on Fermi and Kepler (0x142c) to flush the VBO cache before draw appears to be gone on Maxwell. Is there a replacement method we should use? (Or perhaps that method was never meant for VBO cache flush and instead flushed something related to the vertex quarantine area defined by 0x17bc/0x17c0/0x17c4, which in turn is gone on Maxwell?) Thanks for any light you

Thanks for the update. Are you updating nouveau for GK208 and GM206? Regards, On Tue, Feb 23, 2016 at 4:11 PM, Kyle McMartin <kyle at infradead.org> wrote: > On Tue, Feb 23, 2016 at 06:55:59PM +0900, Alexandre Courbot wrote: > > Hi linux-firmware maintainers, > > > > The following changes since commit > f66eccaab7d605d433cb82e389441b21ec99b40f: > > > >

On Tue, Feb 23, 2016 at 06:55:59PM +0900, Alexandre Courbot wrote: > Hi linux-firmware maintainers, > > The following changes since commit f66eccaab7d605d433cb82e389441b21ec99b40f: > > Update Intel OPA hfi1 firmware (2016-02-15 08:34:16 -0500) > > are available in the git repository at: > > https://github.com/Gnurou/linux-firmware.git secboot > > for you

On Mon, May 19, 2014 at 12:16 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c > index 5871f59..c9ab13a

Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/fb/gm107.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/fb/gm107.c b/drm/nouveau/nvkm/subdev/fb/gm107.c index 2a91df8..9cc7e61 100644 --- a/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -29,7 +29,7 @@ gm107_fb = { .dtor =

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nouveau_copy.c | 2 ++ src/nvc0_accel.c | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index c139de6..7118a7a 100644 --- a/src/nouveau_copy.c +++ b/src/nouveau_copy.c @@ -42,6 +42,8 @@ nouveau_copy_init(ScreenPtr pScreen) int engine; Bool

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Untested. src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 3 +++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 14 insertions(+) diff --git a/src/nouveau_copy.c b/src/nouveau_copy.c index 7118a7a..7fbcc87 100644 --- a/src/nouveau_copy.c

Hello, I got some doubts on how texture modes work on TEX, TEXS, TLD4, etc instructions. I got: DC, AOFFI, NDV, NODEP, MZ, PTP modes as well as LZ Mode. How does this work or change the behavior of the texture instruction. So far of those I know AOFFI defines an Offset but I'm on blanks for the rest. -------------- next part -------------- An HTML attachment was scrubbed... URL:

So I have been going on over the documentation trying to figure out the exact layout of Pitch Linear Textures and find some missing values. First Question: What's the correct layout of pitch linear textures in memory? Is padding of the pitch added at start or at the end? Do they have some kind of header? Currently I see them as a normal texture matrix with just pitch at the end of each row

Signed-off-by: Faris Alsalama <farisbenbrahem at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_backlight.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c index 89eb460..dd1cc9b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_backlight.c +++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c @@ -232,6

0xc0b5 is not in rnndb, I guess it should be GP100_COPY, right? Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com> On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nouveau_copy.c | 2 ++ > src/nvc0_accel.c | 10 +++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- v1 -> v2: add 0x130 as a valid chip type early on in detection src/nouveau_copy.c | 2 ++ src/nouveau_exa.c | 1 + src/nv_accel_common.c | 1 + src/nv_driver.c | 4 ++++ src/nv_type.h | 1 + src/nvc0_accel.c | 6 ++++++ 6 files changed, 15 insertions(+) diff --git a/src/nouveau_copy.c

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c index 5871f59..c9ab13a 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c @@

So we have been busy implementing the compute engine lately but we have discovered a few issues with Compute Shaders. I hope you guys can answer some questions. 1st How do I determine the size of Compute Shaders/Kernel Local Memory ? In Pipeline shaders the size is included in the header but Compute Kernels don't have a header, so how do I determine how much local memory it uses? In case I

So we are currently doing tests and complying with them in our Emulator. Currently the conditional rendering test does not pass (no wonder we not even implement it). I've been looking at the current documentation https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml#L796 So far I don't understand how the cond address is used and to what it's compared.

From: Ben Skeggs <bskeggs at redhat.com> Adds support for the new TIC layout that's present on Maxwell GPUs, heavily based on the code for the existing layout. This code is required for GM20x support. While GM10x supports the older layout still, this commit switches it to use the updated version instead. Piglit testing shows zero regressions on GM107. Signed-off-by: Ben Skeggs