similar to: [PATCH] bsp/g92: disable by default

704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs. g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm. Reported-by: Andrew Randrianasulu <randrianasulu at gmail.com> Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/include/nvkm/subdev/pci.h | 1 + drm/nouveau/nvkm/engine/device/base.c | 20 +++++++-------

Hello all, I am trying to create a corosync/pacemaker cluster using CentOS 6.0. However, I'm having a great deal of difficulty doing so. Corosync has a valid configuration file and an authkey has been generated. When I run /etc/init.d/corosync I see that only corosync is started. >From experience working with corosync/pacemaker before, I know that this is not enough to have a functioning

one rename and one enable patch. Tested on hardware and confirmed with traces Karol Herbst (2): pci: Rename g94 to g92 pci/g92: Enable changing pcie link speeds drm/nouveau/include/nvkm/subdev/pci.h | 2 +- drm/nouveau/nvkm/engine/device/base.c | 22 +++++++++++----------- drm/nouveau/nvkm/subdev/pci/Kbuild | 2 +- drm/nouveau/nvkm/subdev/pci/{g94.c => g92.c} |

https://bugs.freedesktop.org/show_bug.cgi?id=86794 Bug ID: 86794 Summary: Several nouveau related errors with xf86-video-nouveau with NVIDIA G92 [GeForce 9800 GT] and GF108 [GeForce GT 620] (rev a1). Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW

I am stuck. This is X86_64 platform. In the extras repos, there is the SRPMS for heartbeat along with the RPMS for it. I have downloaded both. But I can't build the RPMS from the SRPM as it fails compiling something in BUILD/heartbeat-2.0.8/lib/crm/pengine Additionally, I can't install the RPMS: rpm -Uvh heartbeat-2.0.8-3.el5.centos.i386.rpm heartbeat-2.0.8-3.el5.centos.x86_64.rpm

taken from nvgpu Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 1 + drm/nouveau/nvkm/subdev/pci/pcie.c | 14

https://bugs.freedesktop.org/show_bug.cgi?id=95330 Bug ID: 95330 Summary: [NV84] Hangs with gr: DATA_ERROR [INVALID_BITFIELD], TRAP_PROP [RT_FAULT], fb: trapped write [PGRAPH] [PROP] [RT0] [PAGE_NOT_PRESENT], bsp: Watchdog interrupt, engine hung Product: xorg Version: unspecified

On Fri, 13 Sep 2019 at 05:00, Karol Herbst <kherbst at redhat.com> wrote: > > taken from nvgpu > > Signed-off-by: Karol Herbst <kherbst at redhat.com> > --- > drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ > drm/nouveau/nvkm/subdev/pci/g92.c | 1 + > drm/nouveau/nvkm/subdev/pci/g94.c | 1 + > drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + >

nv92 hardware has only 16 interrupt lines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs at redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable

On Fri, Dec 6, 2013 at 7:36 PM, Benjamin Morris <bmorris at nvidia.com> wrote: > I've gathered a few hints regarding H264 video decoding on our hardware. Hopefully some of them will be useful. Very useful! > > First off, regarding naming in general. Our internal names for our video engines differ from the names you've been using. Below is a translation map between the

On Sat, 30 Nov 2013 12:54:45 -0800 Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Thu, Nov 21, 2013 at 5:22 PM, Ilia Mirkin <imirkin at alum.mit.edu> > wrote: > > On Thu, Nov 21, 2013 at 5:07 PM, Benjamin Morris > > <bmorris at nvidia.com> wrote: > >> On 11/19/2013 08:16 PM, Ilia Mirkin wrote: > >>> Hello, > >>> >

Thomas, Thank you for your reply about the for () loop. The as.character advice worked. Sorry for the delay in getting back to?I had to set the project aside for a few weeks. This didn?t work exactly as is for (patient in as.character(1:n)){ pt <- MRN == patient (rest of the function) } But this did for (patient in as.character(levels(MRN))){ pt <- MRN == patient (rest of the function)

everything was taken from nvgpu. Main reason for adding is to improve stability of the PCIe link changing code as we might want to depend on it for a workaround fixing our infamous runpm issues on recent laptops Karol Herbst (3): pci: force disable ASPM before changing the link speed pci/gk104: enable dl_mgr safe mode pci/gk104: wait for ltssm idle before changing the link

On Fri, Oct 25, 2013 at 7:43 AM, Robert Morell <rmorell at nvidia.com> wrote: > On Mon, Sep 30, 2013 at 10:44:12AM -0700, Lucas Stach wrote: >> Hi, >> >> recently we tried to enable MSI interrupts with nouveau. Unfortunately >> there have been some reports of things failing with certain cards, where >> it isn't entirely clear if this is a GPU errata or

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of

I am looking for feedback to add support for a new loop pragma to Clang/LLVM. With "#pragma tail_predicate" the idea would be to indicate that a loop epilogue/tail can, or should be, folded into the main loop. I see two use cases for this pragma. First, this could be interesting for the vectorizer. It currently supports tail folding by masking all loop instructions/blocks, but does this

On Thu, Oct 24, 2013 at 04:03:12PM -0700, Ben Skeggs wrote: > On Fri, Oct 25, 2013 at 7:43 AM, Robert Morell <rmorell at nvidia.com> wrote: > > On Mon, Sep 30, 2013 at 10:44:12AM -0700, Lucas Stach wrote: > >> Hi, > >> > >> recently we tried to enable MSI interrupts with nouveau. Unfortunately > >> there have been some reports of things failing

--- man/nouveau.man | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/man/nouveau.man b/man/nouveau.man index 7c72907..a8dfacd 100644 --- a/man/nouveau.man +++ b/man/nouveau.man @@ -13,7 +13,7 @@ nouveau \- NVIDIA video driver .fi .SH DESCRIPTION .B nouveau -is an __xservername__ driver for NVIDIA video cards. The driver supports 2D +is an

If I got you right, this is the classic case for loop peeling. I thought LLVM's vectorizer had something like that already in. On 21 July 2013 18:16, Arnold Schwaighofer <aschwaighofer at apple.com> wrote: > I will have to work on this soon as ARM also has pretty inefficient > unaligned vector loads. > NEON does support unaligned access via VLD*/VST*, what loads are you

I merged the both series I sent out recently into one bigger one so that it's more obvious on why all of that is needed. Biggest changes since last sent: * reworked the ASPM patch * removed "pci: add nvkm_pcie_get_speed" patch Please test this on Laptops and report back if it either breaks something or doesn't fix runpm. Thanks Karol Herbst (6): pci: disable ASPM before