similar to: [PATCH] secboot/acr352: reset PMU after secboot

On 07/05/2017 03:35 AM, Karol Herbst wrote: > This is needed for using Nouveaus PMU image after performing secboot. This will > be helpfull for Maxwell2 reclocking on boards without externally controlled > fans like on most laptops or fanless boards. I get the idea in principal, but have some concerns: - Does this screw up re-running secboot during channel recovery (ie. page fault on

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

In case memory resources for *bl_desc* were allocated, release them before return. Addresses-Coverity-ID: 1472021 ("Resource leak") Fixes: 0d466901552a ("drm/nouveau/secboot/acr: Remove VLA usage") Signed-off-by: Gustavo A. R. Silva <gustavo at embeddedor.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 1 + 1 file changed, 1 insertion(+) diff --git

On 8/2/18 12:51 PM, Gustavo A. R. Silva wrote: > Hi all, > > Friendly ping! Who can take this? > > Thanks > -- > Gustavo > > On 07/24/2018 08:27 AM, Gustavo A. R. Silva wrote: >> In case memory resources for *bl_desc* were allocated, release >> them before return. >> >> Addresses-Coverity-ID: 1472021 ("Resource leak") >> Fixes:

In the quest to remove all stack VLA usage from the kernel[1], this allocates the working buffers before starting the writing so it won't abort in the middle. This needs an initial walk of the lists to figure out how large the buffer should be. [1] https://lkml.kernel.org/r/CA+55aFzCG-zNmZwX4A2FQpadafLfEzK6CC=qPXydAacU1RqZWA at mail.gmail.com Signed-off-by: Kees Cook <keescook at

On Fri, Jun 22, 2018 at 10:50 AM, Karol Herbst <kherbst at redhat.com> wrote: > On Thu, May 24, 2018 at 7:24 PM, Kees Cook <keescook at chromium.org> wrote: >> In the quest to remove all stack VLA usage from the kernel[1], this >> allocates the working buffers before starting the writing so it won't >> abort in the middle. This needs an initial walk of the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

Split the reset function into more meaningful and reusable ones. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/secboot.h | 3 ++ drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 78 ++++++++++++++++++++---------- 2 files changed, 56 insertions(+), 25 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/secboot.h

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

ucode_header is not used anywhere, so just get rid of it. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 25 +++++++------------------ drm/nouveau/nvkm/subdev/secboot/ls_ucode.h | 2 -- drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c | 2 -- 3 files changed, 7 insertions(+), 22 deletions(-) diff --git

We accidentally set "psb" which is a no-op instead of "*psb" so it generates a static checker warning. We should probably set it before the first error return so that it's always initialized. Fixes: 923f1bd27bf1 ("drm/nouveau/secboot/gm20b: add secure boot support") Signed-off-by: Dan Carpenter <dan.carpenter at oracle.com> --- Static analysis. I'm

The WPR and LSB headers, used to generate the LS blob, may have a different layout and sizes depending on the driver version they come from. Abstract them and confine their use to driver-specific code. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 102 +++++++++++++--------- drm/nouveau/nvkm/subdev/secboot/acr_r352.h | 119

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

On Thu, May 24, 2018 at 7:24 PM, Kees Cook <keescook at chromium.org> wrote: > In the quest to remove all stack VLA usage from the kernel[1], this > allocates the working buffers before starting the writing so it won't > abort in the middle. This needs an initial walk of the lists to figure > out how large the buffer should be. > > [1]

This was used only locally to one function and can be replaced by ad-hoc variables. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 90 +++++++++++------------------- 1 file changed, 33 insertions(+), 57 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index

Fix sparse warning: drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c:1092:1: warning: symbol 'acr_r352_ls_gpccs_func' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci at huawei.com> Signed-off-by: YueHaibing <yuehaibing at huawei.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)