similar to: How to disable L2 cache on Nvidia GPUs

Dear all, Is there a command or low level instruction to disable the L2 cache in GPUs. Can a certain section of memory be defined as uncachable. Can you please point me the approach to do it. Thank you Vishwas -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/nouveau/attachments/20161107/a1b678b7/attachment.html>

An HTML attachment was scrubbed... URL: <http://lists.xiph.org/pipermail/opus/attachments/20190514/f9c47ab4/attachment-0001.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: 201602111742151_N3WZA6X7.png Type: image/png Size: 33527 bytes Desc: not available URL:

On Thu, Nov 21, 2019 at 1:52 PM Mika Westerberg <mika.westerberg at intel.com> wrote: > > On Thu, Nov 21, 2019 at 01:46:14PM +0200, Mika Westerberg wrote: > > On Thu, Nov 21, 2019 at 12:34:22PM +0100, Rafael J. Wysocki wrote: > > > On Thu, Nov 21, 2019 at 12:28 PM Mika Westerberg > > > <mika.westerberg at intel.com> wrote: > > > > > >

On Wed, Nov 20, 2019 at 11:18 AM Mika Westerberg <mika.westerberg at intel.com> wrote: > > Hi Karol, > > On Tue, Nov 19, 2019 at 11:26:45PM +0100, Karol Herbst wrote: > > On Tue, Nov 19, 2019 at 10:50 PM Bjorn Helgaas <helgaas at kernel.org> wrote: > > > > > > [+cc Dave] > > > > > > On Thu, Oct 17, 2019 at 02:19:01PM +0200, Karol

On Thu, Nov 21, 2019 at 8:49 PM Mika Westerberg <mika.westerberg at intel.com> wrote: > > On Thu, Nov 21, 2019 at 04:43:24PM +0100, Rafael J. Wysocki wrote: > > On Thu, Nov 21, 2019 at 1:52 PM Mika Westerberg > > <mika.westerberg at intel.com> wrote: > > > > > > On Thu, Nov 21, 2019 at 01:46:14PM +0200, Mika Westerberg wrote: > > > > On

On Wed, Nov 20, 2019 at 12:22 PM Mika Westerberg <mika.westerberg at intel.com> wrote: > > On Wed, Nov 20, 2019 at 11:52:22AM +0100, Rafael J. Wysocki wrote: > > On Wed, Nov 20, 2019 at 11:18 AM Mika Westerberg > > <mika.westerberg at intel.com> wrote: > > > > > > Hi Karol, > > > > > > On Tue, Nov 19, 2019 at 11:26:45PM +0100, Karol

On Thu, Nov 21, 2019 at 01:46:14PM +0200, Mika Westerberg wrote: > On Thu, Nov 21, 2019 at 12:34:22PM +0100, Rafael J. Wysocki wrote: > > On Thu, Nov 21, 2019 at 12:28 PM Mika Westerberg > > <mika.westerberg at intel.com> wrote: > > > > > > On Wed, Nov 20, 2019 at 11:29:33PM +0100, Rafael J. Wysocki wrote: > > > > > last week or so I found

so while trying to test with d3cold disabled, I noticed that I run into the exact same error. And I verified that the \_SB.PCI0.PEG0.PG00._STA returns 1, which indicates it should still be turned on. On Thu, Nov 21, 2019 at 11:50 PM Karol Herbst <kherbst at redhat.com> wrote: > > On Thu, Nov 21, 2019 at 11:39 PM Rafael J. Wysocki <rafael at kernel.org> wrote: > > > >

On Wed, Nov 20, 2019 at 4:15 PM Mika Westerberg <mika.westerberg at intel.com> wrote: > > On Wed, Nov 20, 2019 at 01:11:52PM +0100, Karol Herbst wrote: > > On Wed, Nov 20, 2019 at 1:09 PM Mika Westerberg > > <mika.westerberg at intel.com> wrote: > > > > > > On Wed, Nov 20, 2019 at 12:58:00PM +0100, Karol Herbst wrote: > > > > overall,

On Thu, Nov 21, 2019 at 1:52 PM Mika Westerberg <mika.westerberg at intel.com> wrote: > > On Thu, Nov 21, 2019 at 01:46:14PM +0200, Mika Westerberg wrote: > > On Thu, Nov 21, 2019 at 12:34:22PM +0100, Rafael J. Wysocki wrote: > > > On Thu, Nov 21, 2019 at 12:28 PM Mika Westerberg > > > <mika.westerberg at intel.com> wrote: > > > > > >

On Wed, Nov 20, 2019 at 12:58:00PM +0100, Karol Herbst wrote: > overall, what I really want to know is, _why_ does it work on windows? So do I ;-) > Or what are we doing differently on Linux so that it doesn't work? If > anybody has any idea on how we could dig into this and figure it out > on this level, this would probably allow us to get closer to the root > cause? no?

On Fri, Nov 22, 2019 at 11:36 AM Mika Westerberg <mika.westerberg at intel.com> wrote: > > On Thu, Nov 21, 2019 at 11:39:23PM +0100, Rafael J. Wysocki wrote: > > On Thu, Nov 21, 2019 at 8:49 PM Mika Westerberg > > <mika.westerberg at intel.com> wrote: > > > > > > On Thu, Nov 21, 2019 at 04:43:24PM +0100, Rafael J. Wysocki wrote: > > > >

On Fri, Nov 22, 2019 at 12:52 PM Mika Westerberg <mika.westerberg at intel.com> wrote: > [cut] [I'm really running out of time for today, unfortunately.] > > > > The current design is mostly based on the PCI PM Spec 1.2, so it would > > > > be consequent to follow system-wide suspend in PM-runtime and avoid > > > > putting PCIe ports holding

On Wed, Nov 20, 2019 at 01:11:52PM +0100, Karol Herbst wrote: > On Wed, Nov 20, 2019 at 1:09 PM Mika Westerberg > <mika.westerberg at intel.com> wrote: > > > > On Wed, Nov 20, 2019 at 12:58:00PM +0100, Karol Herbst wrote: > > > overall, what I really want to know is, _why_ does it work on windows? > > > > So do I ;-) > > > > > Or what are

On Fri, Nov 22, 2019 at 12:30 PM Rafael J. Wysocki <rafael at kernel.org> wrote: > > On Fri, Nov 22, 2019 at 11:36 AM Mika Westerberg > <mika.westerberg at intel.com> wrote: > > > > On Thu, Nov 21, 2019 at 11:39:23PM +0100, Rafael J. Wysocki wrote: > > > On Thu, Nov 21, 2019 at 8:49 PM Mika Westerberg > > > <mika.westerberg at intel.com>

On Thu, Nov 21, 2019 at 11:39 PM Rafael J. Wysocki <rafael at kernel.org> wrote: > > On Thu, Nov 21, 2019 at 8:49 PM Mika Westerberg > <mika.westerberg at intel.com> wrote: > > > > On Thu, Nov 21, 2019 at 04:43:24PM +0100, Rafael J. Wysocki wrote: > > > On Thu, Nov 21, 2019 at 1:52 PM Mika Westerberg > > > <mika.westerberg at intel.com>

On Wed, Nov 20, 2019 at 12:48 PM Rafael J. Wysocki <rafael at kernel.org> wrote: > > On Wed, Nov 20, 2019 at 12:22 PM Mika Westerberg > <mika.westerberg at intel.com> wrote: > > > > On Wed, Nov 20, 2019 at 11:52:22AM +0100, Rafael J. Wysocki wrote: > > > On Wed, Nov 20, 2019 at 11:18 AM Mika Westerberg > > > <mika.westerberg at intel.com>

On Wed, Nov 20, 2019 at 11:52:22AM +0100, Rafael J. Wysocki wrote: > On Wed, Nov 20, 2019 at 11:18 AM Mika Westerberg > <mika.westerberg at intel.com> wrote: > > > > Hi Karol, > > > > On Tue, Nov 19, 2019 at 11:26:45PM +0100, Karol Herbst wrote: > > > On Tue, Nov 19, 2019 at 10:50 PM Bjorn Helgaas <helgaas at kernel.org> wrote: > > > >

On Mon, Sep 19, 2016 at 11:32:26AM -0400, Frank Myhr wrote: >QEMU's default qcow2 L2 cache size is too small for large images (and small cluster sizes), resulting in very bad performance. > >https://blogs.igalia.com/berto/2015/12/17/improving-disk-io-performance-in-qemu-2-5-with-the-qcow2-l2-cache/ >shows huge performance hit for a 20GB qcow2 with default 64kB cluster size: >

Greetings Please forgive the OT question yet I highly value the experience and wisdom on this list I am wondering if anyone here can address the performance difference between having a processor board with say 256KB L2 *and* 2048KB L3 cache *VERSUS* just having the same processor board with just the L2 cache in a centos server environment... Please figure that all other necessary and related