similar to: [PATCH] drm/nouveau/tegra: Fix error handling

iommu_domain_alloc returns NULL on error so replace an incorrect IS_ERR check with a NULL check. The Coccinelle semantic patch used to find this issue is as follows: @@ expression e; statement S; @@ *e = iommu_domain_alloc(...); if (IS_ERR(e)) S Signed-off-by: Amitoj Kaur Chawla <amitoj1606 at gmail.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 2 +- 1 file changed, 1

In nvkm_device_tegra_probe_iommu(), a paging domain is allocated for @dev and attached to it on success. Use iommu_paging_domain_alloc() to make it explicit. Signed-off-by: Lu Baolu <baolu.lu at linux.intel.com> Link: https://lore.kernel.org/r/20240610085555.88197-7-baolu.lu at linux.intel.com --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 4 ++-- 1 file changed, 2 insertions(+),

From: Wei Yongjun <yongjun_wei at trendmicro.com.cn> In case of error, the function iommu_domain_alloc() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei at trendmicro.com.cn> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 2 +- 1 file changed, 1 insertion(+), 1

In nvkm_device_tegra_probe_iommu(), a paging domain is allocated for @dev and attached to it on success. Use iommu_paging_domain_alloc() to make it explicit. Signed-off-by: Lu Baolu <baolu.lu at linux.intel.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c

On Thu, Sep 05, 2024 at 12:26:31PM -0400, Lyude Paul wrote: > I did take the one patch - but I'm happy to push the others to drm-misc > (provided they all get reviewed. 2/3 seems to be reviewed already but not 3/3) Did it get lost? $ git reset --hard next-20240913 $ git grep 'iommu_domain_alloc(' drivers/gpu/ drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c:

Commit <17de3f5fdd35> ("iommu: Retire bus ops") removes iommu ops from the bus structure. The iommu subsystem no longer relies on bus for operations. So iommu_domain_alloc() interface is no longer relevant. A new helper named iommu_paging_domain_alloc() was introduced in the iommu subsystem as a replacement of iommu_domain_alloc(). This helper relies on the device for IOMMU API

From: Thierry Reding <treding at nvidia.com> If the GPU is already attached to an IOMMU, don't detach it and setup an explicit IOMMU domain. Since Nouveau can now properly handle the case of the DMA API being backed by an IOMMU, just continue using the DMA API. Signed-off-by: Thierry Reding <treding at nvidia.com> --- .../drm/nouveau/nvkm/engine/device/tegra.c | 19

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote: > Hi Thierry, > > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding <treding at nvidia.com> > > > > If the GPU is already attached to an IOMMU, don't detach it and setup an > > explicit IOMMU domain. Since Nouveau can now properly handle the case of > > the DMA API

GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Hi Ben, The DT bindings for this have been approved but not merged yet. This means that for 4.6 GM20B will fail to probe unless the DT is patched - but this is better than the current

Hi Thierry, On 16/09/2019 16:04, Thierry Reding wrote: > From: Thierry Reding <treding at nvidia.com> > > If the GPU is already attached to an IOMMU, don't detach it and setup an > explicit IOMMU domain. Since Nouveau can now properly handle the case of > the DMA API being backed by an IOMMU, just continue using the DMA API. > > Signed-off-by: Thierry Reding

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

On 16/09/2019 16:57, Thierry Reding wrote: > On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote: >> Hi Thierry, >> >> On 16/09/2019 16:04, Thierry Reding wrote: >>> From: Thierry Reding <treding at nvidia.com> >>> >>> If the GPU is already attached to an IOMMU, don't detach it and setup an >>> explicit IOMMU domain. Since

Am Montag, den 25.01.2016, 18:44 +0900 schrieb Alexandre Courbot: > nvkm_device_tegra_new initializes the irq member of the Tegra device > to -1 in order to signal that it is uninitialized. However, > nvkm_device_tegra_fini tests it against 0 to check whether an IRQ has > been allocated or not. This leads to free_irq being called on -1 > during > device initialization. > The

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

nvkm_device_tegra_new initializes the irq member of the Tegra device to -1 in order to signal that it is uninitialized. However, nvkm_device_tegra_fini tests it against 0 to check whether an IRQ has been allocated or not. This leads to free_irq being called on -1 during device initialization. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> ---

On Tegra186 systems with certain firmware revisions, leaving the GPU in reset can cause a hang. To prevent this, don't leave the GPU in reset. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c

From: Thierry Reding <treding at nvidia.com> The nouveau_fence_get_get_driver_name() function has a redundant _get in its name. Remove it. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nouveau_fence.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c

On 06/09/2017 10:25 PM, Mikko Perttunen wrote: > On Tegra186, powergating is handled by the BPMP power domain provider > and the "legacy" powergating API is not available. Therefore skip > these calls if we are attached to a power domain. Thanks Mikko, Taken all 3 patches into my tree. Ben. > > Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> > ---

On Tegra186, powergating is handled by the BPMP power domain provider and the "legacy" powergating API is not available. Therefore skip these calls if we are attached to a power domain. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git