similar to: [PATCH v2 0/7] Add Maxwell support

rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to work. Very lightly tested. Instead of sticking coordinates into pushbufs, the vertex shader is modified to read them from a constbuf, indexed by vertex id. This approach could be used for all nvc0 generations, but I didn't want to rock the boat. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Note: this

rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to work. Very lightly tested. Instead of sticking coordinates into pushbufs, the vertex shader is modified to read them from a constbuf, indexed by vertex id. This approach could be used for all nvc0 generations, but I didn't want to rock the boat. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> ---

Looks reasonable, some minor comments below. On 10/16/2016 02:06 AM, Ilia Mirkin wrote: > rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to > work. Very lightly tested. > > Instead of sticking coordinates into pushbufs, the vertex shader is > modified to read them from a constbuf, indexed by vertex id. This > approach could be used for all nvc0 generations,

Based on the original patch by Christoph Bumiller, but since it depends on kernel support patched I cannot push it yet. The changes are that I enable vblank by default, and offset takes OFFSET_HIGH/LOW instead of something relative to notifier_bo. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- diff --git a/man/nouveau.man b/man/nouveau.man index 7c72907..8765569

These are copied directly from the mesa repository. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++ src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++---------------- 2 files changed, 892 insertions(+), 340 deletions(-) create mode 100644 src/hwdefs/gm107_texture.xml.h diff --git

v4: Updated the wait dependancy bars based on tex component masks. This patch adds proper delays to maxwell exa shaders. Tested with rendercheck -f a8r8g8b8. I am still wondering whether the rd's are required. We could still wait on the write bars instead. eg. see "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp Trello:

Removed explicit depar instructions as they're not used by the blob anymore. Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 5 ++--- src/shader/exac8nv110.fpc | 10 ++++------ src/shader/exacanv110.fp | 5 ++--- src/shader/exacanv110.fpc | 10 ++++------ src/shader/exacmnv110.fp | 5 ++--- src/shader/exacmnv110.fpc | 10 ++++------

This patch adds proper delays to maxwell exa shaders. rendercheck tests seem consistent with/without this patch. I haven't extensively tested them though. Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 10 +++++----- src/shader/exac8nv110.fpc | 18

v2: Add missing delays This patch adds proper delays to maxwell exa shaders. rendercheck tests seem consistent with/without this patch. I haven't extensively tested them though. Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off-by: Aaryaman Vasishta <jem456.vasishta at gmail.com> --- src/shader/exac8nv110.fp | 10 +++++-----

Few comments below. On 10/16/2016 09:14 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ >

On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Nice work! > > See my comments below, and double-check if some of them can be applied to > the shaders I didn't review yet. > > I recommend you to test your work because if one sched code is wrong, you > are likely going to kill your card and reboot your box. :-) > > >

Are you sure this refactoring doesn't break anything? Few comments inline. On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h |

Hi, On Wed, Jun 28, 2017 at 12:53 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > BTW, you can drop those explicit "depbar" ops. I think they're only > needed when you're doing something weird with barriers. Blob doesn't > use them (anymore) > Gotcha. Should I remove them in the same patch or a different one? It seems like the depbar removal is

On Thu, Jun 8, 2017 at 5:01 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > > > On 06/07/2017 06:58 PM, Aaryaman Vasishta wrote: > >> >> >> On Tue, Jun 6, 2017 at 7:15 AM, Samuel Pitoiset < >> samuel.pitoiset at gmail.com <mailto:samuel.pitoiset at gmail.com>> wrote: >> >> Nice work! >> >> See my

On Mon, Oct 17, 2016 at 5:28 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Looks reasonable, some minor comments below. > > > On 10/16/2016 02:06 AM, Ilia Mirkin wrote: >> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c >> index 6add60b..a53dfe6 100644 >> --- a/src/nvc0_exa.c >> +++ b/src/nvc0_exa.c >> @@ -914,14 +914,56 @@

With this patch the DDX almost works with GK20A, the missing piece is adding COHERENT mappings to the right places. ;-) If you specify NOUVEAU_BO_APER the kernel will truncate valid_domains to the domains specified at creation time. This means that as long as we only specify the correct domain in nouveau_allocate_surface the effect is still the same. Signed-off-by: Maarten Lankhorst <dev at

This patch-series implements the ARB_viewport_array for nvc0 and does a little house-cleanig afterwords. Tobias Klausmann (3): nvc0: implement multiple viewports/scissors, enable ARB_viewport_array nvc0: mark scissor in nvc0_clear_{} nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer .../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -

This patch-series implements the ARB_viewport_array for nvc0 and does a little house-cleanig afterwords. V2: Add Release-Notes, mark this in GL3 as done for nvc0 Don't mark the scissors dirty when we don't need to do that Tobias Klausmann (3): nvc0: implement multiple viewports/scissors, enable ARB_viewport_array docs: update GL3.txt, relnotes: mark GL_ARB_viewport_array as done

Generated with envysched. Tested by running rendercheck from piglit, running mplayer -vo xv, and staring at gnome-shell. Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com> --- src/shader/exac8nv110.fp | 11 ++++---- src/shader/exac8nv110.fpc | 22 ++++++++-------- src/shader/exacanv110.fp | 11 ++++---- src/shader/exacanv110.fpc | 22 ++++++++-------- src/shader/exacmnv110.fp | 10

Fixes fbo-drawbuffers-none glClearBuffer piglit test. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Only tested on nv50, but implementations seem similar enough. src/gallium/drivers/nouveau/nv50/nv50_surface.c | 17 +++++++++-------- src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 17 +++++++++-------- 2 files changed, 18 insertions(+), 16 deletions(-) diff --git