similar to: [PATCH 1/2] Revert "bus: remove cpu_coherent flag"

On Sun, Sep 18, 2016 at 7:21 PM, Karol Herbst <karolherbst at gmail.com> wrote: > This reverts commit 01bbcb69f80e1058395b737ae399c6f4ef48691b. > > The commit caused fence timeouts within nvc0_screen_destroy and most likely > other places as well. > > The most obvious effect is, that userspace processes take minutes to actually > quit. Acked-by: Alexandre Courbot

On Sun, Sep 18, 2016 at 11:39 PM, Alexandre Courbot <gnurou at gmail.com> wrote: > On Sun, Sep 18, 2016 at 7:21 PM, Karol Herbst <karolherbst at gmail.com> wrote: >> This reverts commit 01bbcb69f80e1058395b737ae399c6f4ef48691b. I think you meant aff51175cdbf345740ec9203eff88e772af88059 - that's the commit id that matters, not the one in Ben's non-linux repo. >>

TTM-allocated coherent objects were populated using the DMA API and accessed using the mapping it returned to workaround coherency issues. These issues seem to have been solved, thus remove this extra case to handle and use the regular kernel mapping functions. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nouveau_bo.c | 61

From: Robin Murphy <robin.murphy at arm.com> This reverts commit 1733a2ad36741b1812cf8b3f3037c28d0af53f50. There is apparently something amiss with the way the TTM code handles DMA buffers, which the above commit was attempting to work around for arm64 systems with non-coherent PCI. Unfortunately, this completely breaks systems *with* coherent PCI (which appear to be the majority).

On Mon, Sep 19, 2016 at 12:43 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Sun, Sep 18, 2016 at 11:39 PM, Alexandre Courbot <gnurou at gmail.com> wrote: >> On Sun, Sep 18, 2016 at 7:21 PM, Karol Herbst <karolherbst at gmail.com> wrote: >>> This reverts commit 01bbcb69f80e1058395b737ae399c6f4ef48691b. > > I think you meant

On 06/06/16 08:11, Alexandre Courbot wrote: > From: Robin Murphy <robin.murphy at arm.com> > > This reverts commit 1733a2ad36741b1812cf8b3f3037c28d0af53f50. > > There is apparently something amiss with the way the TTM code handles > DMA buffers, which the above commit was attempting to work around for > arm64 systems with non-coherent PCI. Unfortunately, this completely

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

Another revision of this patchset critical for GK20A to operate. Previous attempts were exclusively using either TTM's regular page allocator or the DMA API one. Both have their advantages and drawbacks: the page allocator is fast but requires explicit synchronization on non-coherent architectures, whereas the DMA allocator always returns coherent memory, but is also slower, creates a

Without this buffer inconsistencies may appear between the CPU and GPU when using a PCI GPU on an ARM64 board. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/engine/device/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/device/pci.c b/drm/nouveau/nvkm/engine/device/pci.c index 62ad0300cfa5..18fab3973ce5

This reverts commit 1733a2ad36741b1812cf8b3f3037c28d0af53f50. There is apparently something amiss with the way the TTM code handles DMA buffers, which the above commit was attempting to work around for arm64 systems with non-coherent PCI. Unfortunately, this completely breaks systems *with* coherent PCI (which appear to be the majority). Booting a plain arm64 defconfig + CONFIG_DRM +

Every other *_drm.h does #include "drm.h". Something else is wrong. On Sun, Sep 18, 2016 at 6:21 AM, Karol Herbst <karolherbst at gmail.com> wrote: > Cought while working on travis-ci integration > > Signed-off-by: Karol Herbst <karolherbst at gmail.com> > --- > drm/nouveau/uapi/drm/nouveau_drm.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warning: drivers/gpu/drm/nouveau/nouveau_bo.c:1434:53: warning: this statement may fall through [-Wimplicit-fallthrough=] Warning level 3 was used: -Wimplicit-fallthrough=3 This patch is part of the ongoing efforts to enabling -Wimplicit-fallthrough.

On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote: > On architectures for which access to GPU memory is non-coherent, > caches need to be flushed and invalidated explicitly when BO control > changes between CPU and GPU. > > This patch adds buffer synchronization functions which invokes the > correct API (PCI or DMA) to ensure synchronization is effective. >

Hi, Please drop this, as I have included this fix into the following patch, which addresses all the expected fall-throughs in drivers/gpu/drm: https://lore.kernel.org/patchwork/patch/1042856/ Thanks -- Gustavo On 2/11/19 12:58 PM, Gustavo A. R. Silva wrote: > In preparation to enabling -Wimplicit-fallthrough, mark switch > cases where we are expecting to fall through. > > This

On Thu, May 7, 2020 at 12:11 AM Milan Buska <milan.buska at gmail.com> wrote: > > On 20-05-06 18:53:00, Ilia Mirkin wrote: > > On Wed, May 6, 2020 at 5:59 PM Milan Buska <milan.buska at gmail.com> wrote: > > > > > > On 20-05-06 17:12:44, Ilia Mirkin wrote: > > > > You need both VRAM *and* UNCACHED. Separate them with a | > > > >

Am Mittwoch, den 06.05.2020, 10:26 -0400 schrieb Ilia Mirkin: > [please keep list cc'd in your replies] > > On Wed, May 6, 2020 at 10:15 AM Milan Bu?ka <milan.buska at gmail.com> wrote: > > [ 0.000000] Linux version 5.6.10-zotac (root at saux) (gcc version 9.3.0 (SAUX Aarch64)) #1 SMP PREEMPT Tue May 5 22:16:40 CEST 2020 > > [ 0.000000] Machine model: NVIDIA

On Fri, Jul 11, 2014 at 11:40:27AM +0900, Alexandre Courbot wrote: > On 07/10/2014 10:04 PM, Daniel Vetter wrote: > >On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote: > >>On architectures for which access to GPU memory is non-coherent, > >>caches need to be flushed and invalidated explicitly when BO control > >>changes between CPU and GPU. >

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs. Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/engine/device/base.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 8ebbe1656..37589f365 100644 ---

In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Warning level 3 was used: -Wimplicit-fallthrough=3 Notice that, in some cases, the code comment is modified in accordance with what GCC is expecting to find. This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <gustavo at

Hi guys, I've already send this out in September last year, but only got a response from Daniel. Could you guys please test this and tell me what you think about it? Basically I'm trying to remove all driver specific features from TTM which don't need to be inside the framework. Thanks, Christian.