similar to: [PATCH 1/2] ttm: remove special handling of coherent objects

This reverts commit 01bbcb69f80e1058395b737ae399c6f4ef48691b. The commit caused fence timeouts within nvc0_screen_destroy and most likely other places as well. The most obvious effect is, that userspace processes take minutes to actually quit. Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/include/nvkm/core/device.h | 1 + drm/nouveau/nouveau_bo.c |

On Sun, Sep 18, 2016 at 7:21 PM, Karol Herbst <karolherbst at gmail.com> wrote: > This reverts commit 01bbcb69f80e1058395b737ae399c6f4ef48691b. > > The commit caused fence timeouts within nvc0_screen_destroy and most likely > other places as well. > > The most obvious effect is, that userspace processes take minutes to actually > quit. Acked-by: Alexandre Courbot

On Sun, Sep 18, 2016 at 11:39 PM, Alexandre Courbot <gnurou at gmail.com> wrote: > On Sun, Sep 18, 2016 at 7:21 PM, Karol Herbst <karolherbst at gmail.com> wrote: >> This reverts commit 01bbcb69f80e1058395b737ae399c6f4ef48691b. I think you meant aff51175cdbf345740ec9203eff88e772af88059 - that's the commit id that matters, not the one in Ben's non-linux repo. >>

It has been a couple of months since v4 - apologies for this. v4 has not received many comments, but this version addresses them and makes a new attempt at pushing the critical bit for GK20A and Nouveau on ARM in general. As a reminder, this series addresses the memory coherency issue that we are seeing on ARM platforms. Contrary to x86 which invalidates the PCI caches whenever a write is made by

Another revision of this patchset critical for GK20A to operate. Previous attempts were exclusively using either TTM's regular page allocator or the DMA API one. Both have their advantages and drawbacks: the page allocator is fast but requires explicit synchronization on non-coherent architectures, whereas the DMA allocator always returns coherent memory, but is also slower, creates a

From: Robin Murphy <robin.murphy at arm.com> This reverts commit 1733a2ad36741b1812cf8b3f3037c28d0af53f50. There is apparently something amiss with the way the TTM code handles DMA buffers, which the above commit was attempting to work around for arm64 systems with non-coherent PCI. Unfortunately, this completely breaks systems *with* coherent PCI (which appear to be the majority).

While working on TTM cleanups I've found that the io_reserve_lru used by Nouveau is actually not working at all. In general we should remove driver specific handling from the memory management, so this patch moves the io_reserve_lru handling into Nouveau instead. v2: don't call ttm_bo_unmap_virtual in nouveau_ttm_io_mem_reserve v3: rebased and use both base and offset in the check v4:

From: Christian K?nig <ckoenig.leichtzumerken at gmail.com> While working on TTM cleanups I've found that the io_reserve_lru used by Nouveau is actually not working at all. In general we should remove driver specific handling from the memory management, so this patch moves the io_reserve_lru handling into Nouveau instead. The patch should be functional correct, but is only compile

On Mon, Sep 30, 2019 at 03:12:53PM +0200, Christian König wrote: > While working on TTM cleanups I've found that the io_reserve_lru used by > Nouveau is actually not working at all. > > In general we should remove driver specific handling from the memory > management, so this patch moves the io_reserve_lru handling into Nouveau > instead. > > The patch should be

Without diving in any of the details, your commit message has me curious and concerned... In a "manager" kind of way, despite being neither a manager nor an insider or active contributor. ;-) On 24/01/2020 14:30, Christian K?nig wrote: > From: Christian K?nig <ckoenig.leichtzumerken at gmail.com> > > While working on TTM cleanups I've found that the io_reserve_lru

On Sat, 25 Jan 2020 at 00:30, Christian K?nig <ckoenig.leichtzumerken at gmail.com> wrote: > > From: Christian K?nig <ckoenig.leichtzumerken at gmail.com> > > While working on TTM cleanups I've found that the io_reserve_lru used by > Nouveau is actually not working at all. > > In general we should remove driver specific handling from the memory > management,

On architectures for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly when BO control changes between CPU and GPU. This patch adds buffer synchronization functions which invokes the correct API (PCI or DMA) to ensure synchronization is effective. Based on the TTM DMA cache helper patches by Lucas Stach. Signed-off-by: Lucas Stach <dev at

While working on TTM cleanups I've found that the io_reserve_lru used by Nouveau is actually not working at all. In general we should remove driver specific handling from the memory management, so this patch moves the io_reserve_lru handling into Nouveau instead. The patch should be functional correct, but is only compile tested! Signed-off-by: Christian König <christian.koenig at

On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote: > On architectures for which access to GPU memory is non-coherent, > caches need to be flushed and invalidated explicitly when BO control > changes between CPU and GPU. > > This patch adds buffer synchronization functions which invokes the > correct API (PCI or DMA) to ensure synchronization is effective. >

Introduce accessors for TTM buffer object memory that has been mapped into the kernel virtual address space or as IO memory. IO memory needs to be accessed via special accessor functions, not by dereferencing the iomem cookie. The wrappers hide the details of 32-bit access and honour the TTM map type. nv04_crtc_cursor_set() is changed to use the new wrappers. 'cursor' is received from

On 07/10/2014 10:04 PM, Daniel Vetter wrote: > On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote: >> On architectures for which access to GPU memory is non-coherent, >> caches need to be flushed and invalidated explicitly when BO control >> changes between CPU and GPU. >> >> This patch adds buffer synchronization functions which invokes the >>

On Fri, Jul 11, 2014 at 11:40:27AM +0900, Alexandre Courbot wrote: > On 07/10/2014 10:04 PM, Daniel Vetter wrote: > >On Tue, Jul 08, 2014 at 05:25:59PM +0900, Alexandre Courbot wrote: > >>On architectures for which access to GPU memory is non-coherent, > >>caches need to be flushed and invalidated explicitly when BO control > >>changes between CPU and GPU. >

From: Maarten Lankhorst <maarten.lankhorst at canonical.com> Map the GART to the bar and use that mapping, to hide all the tiling details from users. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com> --- drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c | 5 ++++- drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | 5 ++++- drivers/gpu/drm/nouveau/nouveau_bo.c

On Mon, May 19, 2014 at 11:22:11AM +0200, Lucas Stach wrote: > Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: > > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: > > > Some architectures (e.g. ARM) need the CPU buffers to be explicitely > > > flushed for a memory write to take effect. Not doing so results in > > >

Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: > > Some architectures (e.g. ARM) need the CPU buffers to be explicitely > > flushed for a memory write to take effect. Not doing so results in > > synchronization issues, especially after writing to BOs. > > It seems to me that the above