similar to: [PATCH v2] instmem/gk20a: set DMA mask early

GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Hi Ben, The DT bindings for this have been approved but not merged yet. This means that for 4.6 GM20B will fail to probe unless the DT is patched - but this is better than the current

DMA mask is typically set in nouveau_ttm_init(), but this function is called late during initialization and GK20A's instmem will have called DMA functions before this happens. Having a wrongly set DMA mask can result in the use of unneeded bounce buffers. Set it in GK20A's instmem constructor to avoid this. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> ---

After long term efforts of fixing non-common clock implementations, clk_disable() is a no-op for a NULL pointer input, and this is now tree-wide consistent. All clock consumers can safely call clk_disable(_unprepare) without NULL pointer check. Signed-off-by: Masahiro Yamada <yamada.masahiro at socionext.com> --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 15 +++++----------

From: Thierry Reding <treding at nvidia.com> If the GPU is already attached to an IOMMU, don't detach it and setup an explicit IOMMU domain. Since Nouveau can now properly handle the case of the DMA API being backed by an IOMMU, just continue using the DMA API. Signed-off-by: Thierry Reding <treding at nvidia.com> --- .../drm/nouveau/nvkm/engine/device/tegra.c | 19

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

Hi Thierry, On 16/09/2019 16:04, Thierry Reding wrote: > From: Thierry Reding <treding at nvidia.com> > > If the GPU is already attached to an IOMMU, don't detach it and setup an > explicit IOMMU domain. Since Nouveau can now properly handle the case of > the DMA API being backed by an IOMMU, just continue using the DMA API. > > Signed-off-by: Thierry Reding

On 11/11/2015 06:07 PM, Alexandre Courbot wrote: > Commit 69c4938249fb ("drm/nouveau/instmem/gk20a: use direct CPU access") > tried to be smart while using the DMA-API by managing the CPU mappings of > buffers allocated with the DMA-API by itself. In doing so, it relied > on dma_to_phys() which is an architecture-private function not > available everywhere. This broke the

On Tegra186, powergating is handled by the BPMP power domain provider and the "legacy" powergating API is not available. Therefore skip these calls if we are attached to a power domain. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git

Commit 69c4938249fb ("drm/nouveau/instmem/gk20a: use direct CPU access") tried to be smart while using the DMA-API by managing the CPU mappings of buffers allocated with the DMA-API by itself. In doing so, it relied on dma_to_phys() which is an architecture-private function not available everywhere. This broke the build on several architectures. Since there is no reliable and portable

On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote: > Hi Thierry, > > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding <treding at nvidia.com> > > > > If the GPU is already attached to an IOMMU, don't detach it and setup an > > explicit IOMMU domain. Since Nouveau can now properly handle the case of > > the DMA API

On 16/09/2019 16:57, Thierry Reding wrote: > On Mon, Sep 16, 2019 at 04:29:18PM +0100, Robin Murphy wrote: >> Hi Thierry, >> >> On 16/09/2019 16:04, Thierry Reding wrote: >>> From: Thierry Reding <treding at nvidia.com> >>> >>> If the GPU is already attached to an IOMMU, don't detach it and setup an >>> explicit IOMMU domain. Since

On Tegra186 systems with certain firmware revisions, leaving the GPU in reset can cause a hang. To prevent this, don't leave the GPU in reset. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c

Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc:

On 06/09/2017 10:25 PM, Mikko Perttunen wrote: > On Tegra186, powergating is handled by the BPMP power domain provider > and the "legacy" powergating API is not available. Therefore skip > these calls if we are attached to a power domain. Thanks Mikko, Taken all 3 patches into my tree. Ben. > > Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> > ---

These 4 patches fix two issues that existed on Tegra regarding DMA: 1) The bit indicating whether to use an IOMMU or not was hardcoded ; make this a platform property and use it in instmem 2) The DMA mask was not set for platform devices. Fix this by converting more pci_dma* to the DMA API, and use that more generic code to set the DMA mask properly for all platforms. Tested on both x86

Am Montag, den 25.01.2016, 18:44 +0900 schrieb Alexandre Courbot: > nvkm_device_tegra_new initializes the irq member of the Tegra device > to -1 in order to signal that it is uninitialized. However, > nvkm_device_tegra_fini tests it against 0 to check whether an IRQ has > been allocated or not. This leads to free_irq being called on -1 > during > device initialization. > The

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

From: Thierry Reding <treding at nvidia.com> Depending on the kernel configuration, early ARM architecture setup code may have attached the GPU to a DMA/IOMMU mapping that transparently uses the IOMMU to back the DMA API. Tegra requires special handling for IOMMU backed buffers (a special bit in the GPU's MMU page tables indicates the memory path to take: via the SMMU or directly to the

In nvkm_device_tegra_probe_iommu(), a paging domain is allocated for @dev and attached to it on success. Use iommu_paging_domain_alloc() to make it explicit. Signed-off-by: Lu Baolu <baolu.lu at linux.intel.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c

In nvkm_device_tegra_probe_iommu(), a paging domain is allocated for @dev and attached to it on success. Use iommu_paging_domain_alloc() to make it explicit. Signed-off-by: Lu Baolu <baolu.lu at linux.intel.com> Link: https://lore.kernel.org/r/20240610085555.88197-7-baolu.lu at linux.intel.com --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 4 ++-- 1 file changed, 2 insertions(+),