similar to: [PREVIEW] GM200/GM204 signed firmware for Nouveau

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

Hi everyone, This email is to start a discussion about the format into which NVIDIA firmware is going to be provided. If you had a look at the linux-firmware branch we pushed earlier [1] you may already have an idea of the general organization, but this email is to discuss more specific details. Official firmware is organized per-chip, with an additional level of hierarchy for the different

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/secboot.h | 2 + drm/nouveau/nvkm/engine/device/base.c | 2 + drm/nouveau/nvkm/engine/gr/gm200.c | 8 +-

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

Hi linux-firmware maintainers, The following changes since commit f66eccaab7d605d433cb82e389441b21ec99b40f: Update Intel OPA hfi1 firmware (2016-02-15 08:34:16 -0500) are available in the git repository at: https://github.com/Gnurou/linux-firmware.git secboot for you to fetch changes up to 8d1fd61a3723ab8cb6b7bfeb8be38e16282cc1ed: nvidia: Add GM20B signed firmware (2016-02-23

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

This series fixes two cases where behavior on secure boot errors could be improved: 1) Patch 2 propages secure-boot errors from GR init, making sure initialization fails as it should. Failure to do so results in a black screen during boot, as reported in FD bug 94990. 2) Patches 3-4 make the absence of required secure firmware files a non-fatal error. The previous behavior was to give up

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > The GPUs found on Tegra SoCs have registers that can be used to read the > WPR configuration. Use these registers instead of reaching into the > memory controller's register space to read the same information. > >

On 02/18/2016 12:47 PM, Ilia Mirkin wrote: > On Wed, Feb 17, 2016 at 10:39 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: >> Hi everyone, >> >> This email is to start a discussion about the format into which NVIDIA >> firmware is going to be provided. If you had a look at the linux-firmware >> branch we pushed earlier [1] you may already have an idea

On 02/18/2016 02:37 PM, Ilia Mirkin wrote: > On Thu, Feb 18, 2016 at 12:06 AM, Alexandre Courbot <acourbot at nvidia.com> wrote: >> On 02/18/2016 12:47 PM, Ilia Mirkin wrote: >>> >>> On Wed, Feb 17, 2016 at 10:39 PM, Alexandre Courbot <acourbot at nvidia.com> >>> wrote: >>>> >>>> Hi everyone, >>>> >>>>

On 02/18/2016 02:54 PM, Ilia Mirkin wrote: > On Thu, Feb 18, 2016 at 12:43 AM, Alexandre Courbot <acourbot at nvidia.com> wrote: >> On 02/18/2016 02:37 PM, Ilia Mirkin wrote: >>> >>> On Thu, Feb 18, 2016 at 12:06 AM, Alexandre Courbot <acourbot at nvidia.com> >>> wrote: >>>> >>>> On 02/18/2016 12:47 PM, Ilia Mirkin wrote:

The state of the falcons was not properly updated after running the unload ACR, which caused it to be run again (and thus fail) when nvkm_secboot_fini() was called during resume. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Ben, please feel free to squash this into the gm200 secboot implementation patch - this fixes a bug that should not have been here to begin with.

This allows to have the related MODULE_FIRMWARE tag only on relevant arch (arm64). This will saves about 400k on initramfs when not relevant Signed-off-by: Nicolas Chauvet <kwizart at gmail.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp10b.c | 2 ++ 2 files changed, 4 insertions(+) diff --git

The WPR and LSB headers, used to generate the LS blob, may have a different layout and sizes depending on the driver version they come from. Abstract them and confine their use to driver-specific code. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 102 +++++++++++++--------- drm/nouveau/nvkm/subdev/secboot/acr_r352.h | 119

Split the reset function into more meaningful and reusable ones. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/subdev/secboot.h | 3 ++ drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 78 ++++++++++++++++++++---------- 2 files changed, 56 insertions(+), 25 deletions(-) diff --git a/drm/nouveau/include/nvkm/subdev/secboot.h