similar to: [PATCH] pmu: use nvkm_msec instead of do while

I hit this while loop in an error state of the gpu v2: unlock mutex only if reply == true Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/base.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/base.c b/drm/nouveau/nvkm/subdev/pmu/base.c index 81a5583..eb248fd 100644 ---

> Emil Velikov <emil.l.velikov at gmail.com> hat am 14. November 2015 um 23:44 > geschrieben: > > On 14 November 2015 at 19:51, Karol Herbst <nouveau at karolherbst.de> wrote: > > I hit this while loop in an error state of the gpu > > > > v2: unlock mutex only if reply == true > > > > Signed-off-by: Karol Herbst <nouveau at

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame

I encountered while stresstesting the reclocking code, that rarely (1 out of 20.000+ requests) we don't get any IRQ in nvkm_pmu_intr. This means we have a queued message on the pmu, but nouveau doesn't read it and waits infinitely in nvkm_pmu_send: if (reply) { wait_event(pmu->recv.wait, (pmu->recv.process == 0)); therefore let us use wait_event_timeout with a 1s timeout frame

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). Warn when locking fails. Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 15 ++++++++++++--- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 15 ++++++++++++--- 2 files changed, 24

Corresponds with GT215. Don't rely on the lock test logic being unconditionally enabled, and disable test logic when done (presumably to save power). v2: Remove warning, nvkm_msec already warns on time-out Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 8 +++++++- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 8 +++++++- 2

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Both patches should make the communicating with the PMU more stable. Karol Herbst (2): pmu: fix queued messages while getting no IRQ pmu: be more strict about locking drm/nouveau/nvkm/subdev/pmu/base.c | 49 ++++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) -- 2.7.2

Allow fecs to potentially set both methods: - 0x38 STOP_CTXSW - 0x39 START_CTXSW At present the code only ever starts context swap, and never pauses it as appears to be the intent of one caller of gf100_gr_fecs_ctrl_ctxs(). Cc: Ben Skeggs <bskeggs at redhat.com> Fixes: 2642e0b5 ("gr/gf100-: expose fecs methods for pausing ctxsw") Signed-off-by: Rhys Kidd <rhyskidd at

On 3 September 2015 at 16:42, Alexandre Courbot <acourbot at nvidia.com> wrote: > Allow clients to manually flush and invalidate L2. This will be useful > for Tegra systems for which we want to write instmem using the CPU. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drm/nouveau/include/nvkm/subdev/ltc.h | 1 + >

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drm/nouveau/nvkm/engine/gr/gf100.c | 81 +++++++++++++++++++++++++++++++++----- 1 file changed, 71 insertions(+), 10 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c index 414521b..794e249 100644 --- a/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drm/nouveau/nvkm/engine/gr/gf100.c @@

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- v1 -> v2: undo slight change to SKED stat handling, which would cause writes where there previously might not have been any. drm/nouveau/nvkm/engine/gr/gf100.c | 78 +++++++++++++++++++++++++++++++++----- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c

From: Karol Herbst <git at karolherbst.de> --- drm/nouveau/include/nvif/device.h | 1 + drm/nouveau/include/nvkm/subdev/pmu.h | 10 ++++++++++ drm/nouveau/nouveau_debugfs.c | 23 +++++++++++++++++++++++ drm/nouveau/nvkm/subdev/pmu/base.c | 18 ++++++++++++++++++ 4 files changed, 52 insertions(+) diff --git a/drm/nouveau/include/nvif/device.h

From: Karol Herbst <git at karolherbst.de> v2: optimize macro and fixed data array type --- drm/nouveau/include/nvif/device.h | 1 + drm/nouveau/include/nvkm/subdev/pmu.h | 10 ++++++++++ drm/nouveau/nouveau_debugfs.c | 23 +++++++++++++++++++++++ drm/nouveau/nvkm/subdev/pmu/base.c | 18 ++++++++++++++++++ 4 files changed, 52 insertions(+) diff --git

From: Karol Herbst <git at karolherbst.de> v2: optimize macro and fixed data array type v3: fix bug I added in the last version --- drm/nouveau/include/nvif/device.h | 1 + drm/nouveau/include/nvkm/subdev/pmu.h | 10 ++++++++++ drm/nouveau/nouveau_debugfs.c | 23 +++++++++++++++++++++++ drm/nouveau/nvkm/subdev/pmu/base.c | 18 ++++++++++++++++++ 4 files changed, 52

On Mon, Oct 26, 2015 at 2:13 PM, Karol Herbst <nouveau at karolherbst.de> wrote: > From: Karol Herbst <git at karolherbst.de> > > --- > drm/nouveau/include/nvif/device.h | 1 + > drm/nouveau/include/nvkm/subdev/pmu.h | 10 ++++++++++ > drm/nouveau/nouveau_debugfs.c | 23 +++++++++++++++++++++++ > drm/nouveau/nvkm/subdev/pmu/base.c | 18

Signed-off-by: Roy Spliet <nouveau at spliet.org> --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 8 +++ drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 66 +++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h

Signed-off-by: Roy Spliet <nouveau at spliet.org> Tested-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 128 +++++++++++++++++----- 2 files changed, 99 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h

GR is similar to GP100, with a few unavailable registers. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/include/nvkm/engine/gr.h | 1 + drm/nouveau/nvkm/engine/gr/Kbuild | 1 + drm/nouveau/nvkm/engine/gr/gf100.h | 4 +++ drm/nouveau/nvkm/engine/gr/gp100.c | 13 ++++++-- drm/nouveau/nvkm/engine/gr/gp102.c | 1 + drm/nouveau/nvkm/engine/gr/gp10b.c |