similar to: [PATCH] nvkm: add/remove 0's to make 7 (or 9)-nibble constants use 8 nibbles

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/core/include/subdev/pwr.h | 2 + drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h | 16 ++ drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | 318 +++++++++++++++++++-- .../gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc | 111 +++++++ drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h | 5 +

From: Markus Elfring <elfring at users.sourceforge.net> Date: Wed, 21 Sep 2016 08:28:08 +0200 Do not use curly brackets at four source code places where a single statement should be sufficient. Signed-off-by: Markus Elfring <elfring at users.sourceforge.net> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-)

On Fri, Apr 25, 2014 at 5:19 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: > Changes since v2: > - Enabled software class > - Removed unneeded changes to nouveau_accel_init() > - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with > the portable page_to_phys()/phys_to_page() page_to_phys() looks well defined and used everywhere, phys_to_page() not

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

Changes since v2: - Enabled software class - Removed unneeded changes to nouveau_accel_init() - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with the portable page_to_phys()/phys_to_page() - Fixed incorrect comment/commit log talking about bytes instead of words Hope this looks good! Once this gets merged the next set will be to use this driver on Jetson and Venice2

https://bugzilla.mindrot.org/show_bug.cgi?id=2212 Bug ID: 2212 Summary: openssl version check should ignore status nibble Product: Portable OpenSSH Version: 6.5p1 Hardware: All OS: All Status: NEW Severity: enhancement Priority: P5 Component: Miscellaneous Assignee:

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid

Signed-off-by: Roy Spliet <rspliet at eclipso.eu> --- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c | 6 ++++-- 4 files changed, 9 insertions(+), 3 deletions(-) diff --git

Adds reclocking for NVA0, and a whole lot of work for other cards. Had these patches collecting dust for a little, but tested them with both my NVA0, and Martin's a while back. Success not guaranteed, but should be quite a leap forward. Happy reviewing and testing. Cheers, Roy

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

In bulletpoints: - Add some support for G94 and G96 reclocking. Has been tested on literally two cards, which is hardly adequate as "full coverage". On the other hand, the changes were small enough to make me confident this might work for others as well. - Fix NV50 wait for VBLANK when no monitor is plugged in. - Voltage related inprovements for GT21x. - Slightly improve Keplers

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

Second version of this patchset. Not many changes since first version - I hope this means the changes are not too controversial. Changes since v1: - Removed lookup for previous FW files in "nouveau/" - Went back to using request_firmware() since we only try to load one file Original cover letter follows: GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support

I am a little unsure about the change in nouveau_fence, maybe somebody with more knowledge about the code can look into it? Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/dispnv04/arb.c | 6 ++---- drm/nouveau/nouveau_fence.c | 2 -- drm/nouveau/nvkm/subdev/fb/ramgk104.c | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git

From: Colin Ian King <colin.king at canonical.com> There is a spelling mistake in a nvkm_debug message. Fix it. Signed-off-by: Colin Ian King <colin.king at canonical.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

Probably want ULL for 32-bit arches to be correct here too. On Tue, Dec 31, 2019 at 3:53 PM Wambui Karuga <wambui.karugax at gmail.com> wrote: > > Explicitly declare constants are unsigned long to address the following > sparse warnings: > warning: constant is so big it is long > > Signed-off-by: Wambui Karuga <wambui.karugax at gmail.com> > --- >

Patch 1 fixes nva3 bailing due to not finding the right ramcfg Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period Patch 3-5 handle writes to per-partition registers, for which NVA3 does not have special broadcast regs available. Patch 6 removes local structs from NVA3 reclocking in favour of the already existing "ram->base." variables, like in NVE0 As always,

Hello everyone, GM20B is the GPU of the upcoming Tegra X1 SoC. This series adds initial support for it, based on a rework of the already-supported GK20A. It also introduces support for NVIDIA-provided firmware files, which is why I have added a few NVIDIA people who are relevant to this discussion. The first patch adds support for loading the FECS and GPCCS firmwares from firmware files

"hiding" unconditional assignments in the if() parentesis makes for hard to read code and has no advantage over placing these assignments in proper formated lines before the if() statement. Simply move those lines out. Before sending out roughly 20 patches to fix the roughly 50 cases - all in the nouveau driver. I would like to know if this will be accepted at all. Signed-off-by:

Op 14-09-14 om 10:31 schreef poma: > On 13.09.2014 23:45, Roy Spliet wrote: >> Dear Poma, >> >> Don't get anyone wrong, your input is greatly valued. The reason why >> "we" (nouveau developers) generally ask for a git bisection is because >> we don't know or track specific distributions. Although your search has >> narrowed the problem down