Displaying 20 results from an estimated 500 matches similar to: "Understanding SlotIndexes"
2016 Dec 25
0
Understanding SlotIndexes
On 12/22/2016 4:02 PM, via llvm-dev wrote:
>
> /// Early-clobber register use/def slot. A live range defined at
> /// Slot_EarlyCLobber interferes with normal live ranges killed at
> /// Slot_Register. Also used as the kill slot for live ranges tied to an
> /// early-clobber def.
> Slot_EarlyClobber,
>
> What does this mean, exactly? My
2014 Dec 09
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Jonas,
Thanks for your patience.
After spending some time looking at the additional output you gave me, I agree that your fix is the right one.
I was worried that this problem may arise because we were spilling not real user, but in fact what I thought was the problem is an optimization we could do :).
See my comments inlined for a few nitpicks before you commit.
Thanks again,
-Quentin
On
2012 Sep 20
2
[LLVMdev] InlineSpiller Questions
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes:
>> Are all of those sibling values guaranteed to ultimately derive from the
>> same def, in the sense that they can be traced through copies, phis,
>> etc. back to a single instruction?
>
> They are known the all come from the same value in the original live range from before live range splitting.
Ok, that's
2016 Nov 27
5
Extending Register Rematerialization
Hello LLVM Developers,
We are working on extending currently available register rematerialization
to include cases where sequence of multiple instructions is required to
rematerialize a value.
We had a discussion on this in community mailing list and link is here:
http://lists.llvm.org/pipermail/llvm-dev/2016-September/subject.html#104777
>From the above discussion and studying the code we
2014 Nov 21
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Quentin,
I have tried to find a test case for an official target, but failed. It seems to be a rare case.
To do it, I added the 'else' clause in the following:
...
if (VNI->def == OrigVNI->def) {
DEBUG(dbgs() << "orig phi value\n");
SVI->second.DefByOrigPHI = true;
SVI->second.AllDefsAreReloads = false;
propagateSiblingValue(SVI);
continue;
2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Quentin,
I have rerun the test case on a recent commit, so the numbers have changed. There are also now a few more basic blocks very small basic blocks in the function, and therefore there are some slight differences. I tried to go back to earlier commits, without success for some reason... This is however very similar, except that there becomes two COPYs back to sibling value after the loop.
2014 Nov 18
3
[LLVMdev] InlineSpiller.cpp bug?
Hi,
I have encountered a test case where InlineSpiller generates bad code. A register is reloaded but never spilled, and I suspect a bug in InlineSpiller.
A register is live over a loop that also have two inner loops. It is not used or defined over the inner loops. It is split into two sibling registers, where one covers just the inner loops interval, which is then spilled.
In spill(),
2007 Sep 25
2
[LLVMdev] Coalescing and VNInfo
I've hit a bug in a refactored version of coalescing and I'm trying to
understand what is going on. In particular, I'm curious about this
line in SimpleRegisterCoalescing.cpp:
00710 LHSValsDefinedFromRHS[VNI] =
RHS.getLiveRangeContaining(VNI->def-1)->valno;
Why VNI->def-1? The bug I'm seeing is that RHS returns a NULL
LiveRange because it doesn't contain
2007 Sep 25
0
[LLVMdev] Coalescing and VNInfo
On Tuesday 25 September 2007 10:49, David Greene wrote:
> I've hit a bug in a refactored version of coalescing and I'm trying to
> understand what is going on. In particular, I'm curious about this
> line in SimpleRegisterCoalescing.cpp:
>
> 00710 LHSValsDefinedFromRHS[VNI] =
> RHS.getLiveRangeContaining(VNI->def-1)->valno;
>
> Why VNI->def-1?
2011 Dec 03
1
[LLVMdev] New strict-aliasing warning?
When compiling trunk using gcc 4.1.2 on linux/ppc64, I now see a warning
that I don't remember seeing previously:
llvm[2]: Compiling InlineSpiller.cpp for Release+Asserts build
/src/llvm-trunk-dev/include/llvm/ADT/PointerIntPair.h: In member
function ‘const PointerTy* llvm::PointerIntPair<PointerTy, IntBits,
IntType, PtrTraits>::getAddrOfPointer() const [with PointerTy = void*,
unsigned
2007 Sep 25
2
[LLVMdev] Coalescing and VNInfo
LLVM is assuming this:
struct InstrSlots {
enum {
LOAD = 0,
USE = 1,
DEF = 2,
STORE = 3,
NUM = 4
};
So VNI->def is always modulo 2. For coalescing, it's checking if the
RHS is live at the "use" cycle. So it's checking VNI->def-1.
Evan
On Sep 25, 2007, at 8:55 AM, David Greene wrote:
> On Tuesday
2008 Jan 17
1
[LLVMdev] LiveInterval Questions
On Thursday 17 January 2008 13:03, Evan Cheng wrote:
> > So why does the live range extend throughout the entire basic block?
> >
> > %reg1055 doesn't appear anywhere else in the program so it shouldn't
> > be
> > live-in to the block.
>
> It could be a bug. Can you get me a test case?
I'll see if I can whittle it down. It's a pretty huge
2008 Jan 29
2
[LLVMdev] Possible LiveInterval Bug
I just ran into a problem here. I'm in SimpleRegisterCoalescing at the point
where EXTRACT_SUBREG coalescing updates live ranges of aliased
registers (around line 473 of SimpleRegisterCoalescing.cpp).
There's a call to MergeValueInAsValue at line 50. MergeValueInAsValue has
this code:
void LiveInterval::MergeValueInAsValue(const LiveInterval &RHS,
2007 Sep 25
0
[LLVMdev] Coalescing and VNInfo
On Tuesday 25 September 2007 12:25, Evan Cheng wrote:
> LLVM is assuming this:
> struct InstrSlots {
> enum {
> LOAD = 0,
> USE = 1,
> DEF = 2,
> STORE = 3,
> NUM = 4
> };
>
> So VNI->def is always modulo 2. For coalescing, it's checking if the
> RHS is live at the "use"
2007 Sep 25
1
[LLVMdev] Coalescing and VNInfo
On Tuesday 25 September 2007 13:28, David Greene wrote:
> > So VNI->def is always modulo 2. For coalescing, it's checking if the
> > RHS is live at the "use" cycle. So it's checking VNI->def-1.
>
> But why is it looking at a use slot in this case, where the coalescer is
> trying to get the vaue number for the def of the RHS register so it can
> use
2009 Jan 30
1
[LLVMdev] Question about VNInfo updates by LiveIntervals::addIntervalsForSpills
Hi,
It looks like LiveIntervals::addIntervalsForSpills does not update all
of the LiveIntervals infos quite correctly.
In particular, if a live interval L is defined by Reg<-Reg copy
instructions whose srcReg is later spilled by the
addIntervalsForSpills() function, its VNInfo information is not
updated in a proper way. It still points to the same MachineInstr as
before, even though the
2012 Jul 15
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
I think I'm getting a bit closer to the problem. I've found that the call
to InlineSpiller::foldMemoryOperand() inside
InlineSpiller::spillAroundUses() is causing the problems.
As a test, I removed that call and with your yesterday's patch I'm not
getting any errors at all, the code generated is the same one as with the
call. This is happening when
2010 Aug 09
0
[LLVMdev] MmapAllocator
On Aug 8, 2010, at 9:20 PM, Reid Kleckner wrote:
> I thought I dug into the register allocation code, and found the
> VNInfo::Allocator typedef. I assumed that was getting the traffic we
> saw in Instruments, but I don't have the data to back that up.
Are you using llvm from trunk? VNInfo is a lot smaller now than it was in 2.7. I would guess about a third of the liveness memory
2010 Aug 09
5
[LLVMdev] MmapAllocator
On Sun, Aug 8, 2010 at 8:20 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
>
> On Aug 7, 2010, at 7:05 PM, Steven Noonan wrote:
>> I've been doing work on memory reduction in Unladen Swallow, and
>> during testing, LiveRanges seemed to be consuming one of the largest
>> chunks of memory.
>
> That's interesting. How did you measure this? I'd
2008 Jan 17
0
[LLVMdev] LiveInterval Questions
On Jan 16, 2008, at 11:49 AM, David Greene wrote:
> I had been assuming that give a LiveRange a, a.valno->def, if
> valid, would be the same as a.start. But this is apparently not
> always the case. For example:
>
> Predecessors according to CFG: 0x839d130 (#3) 0x8462780 (#35)
> 308 %reg1051 = MOV64rr %reg1227<kill>
> 312 %reg1052 = MOV64rr %reg1228<kill>