similar to: Instruction selection problem with type i64 - mistaken as v8i64?

Hi, I vaguely remember hitting something like this when I was implementing MSA. IIRC, there was an optimization (in DAGCombine or somewhere around there) that was folding CopyToReg instructions into the load without checking whether the new register class was acceptable. I remember adding a target hook to limit this optimization based on the EVT's involved but I'm not sure if that's

Hello, I'm having problems getting my samba setup to work at a little LAN i partially maintain. I've been reading quite a lot about what I could think of being related to my problems/setup, and I've also googled my ass off :( So here I am, resorting to you guys in hope of help =] Sorry to say, but I don't have much experience, and therefore I'm a bit lost at the moment. Not

Hi all, I've done a simple function for import files but can't do the same think for export files. Could you help me solve it? Thanks in advance for your cooperation. wd<-"C:\\Teste" import<-function(wd0){ wd1<-paste(wd,wd0,"Input\\.", sep = "\\") d<-read.table(choose.files(default = wd1, caption =

I'd like to to put the hard drives in standby mode during periods of no activity. I'm just running a file server plus a couple small things on a Qube 3 from home, although the web stuff will increase it's still minimal. On my NetBSD systems I can use atactl to do this via: mount -u -o async,noatime,nodevmtime / mount -u -o async,noatime /usr atactl wd0 setidle 5 [wait a time]

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return

Hello. I'm having problems at instruction selection with my back end with the following basic-block due to a vector add with immediate constant vector (obtained by vectorizing a simple C program doing vector sum map): vector.ph: ; preds = %vector.memcheck50 %.splatinsert = insertelement <8 x i64> undef, i64 %i.07.unr, i32 0

Hello all! Actually I use dual boot PC with CentOS4 (kernel 2.6.9-11) and WinXP (HDD 20GB, 512MB, PentiumIII 800MHz), but I have the following problem doing the image with g4u ----BEGIN ERROR MESSAGGE---- wd0: (uncorrectable data error) 8951MB 1.59MB/s wd0d: error reading fsbn 18333440 of 18333440 - 18333567 (wd0 bn 18333440; cn 18187 tn 14 sn 62) retrying wd0: (uncorrectable data error)

This post is related to the following post http://lists.llvm.org/pipermail/llvm-dev/2016-April/098823.html I'm still trying to compile a library with clang. But now I'm getting as assert in lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT) const: Assertion `!VT.isVector() && "No default

I am hoping that someone can offer advice on a somewhat unusual issue that I am facing with the SDAG. Namely, I am trying to implement some custom operations that do very specific things on multiple registers at a time. The operations themselves will simply be intrinsics since there are no equivalent operations in IR/SDAG. However, handling the types seems rather tricky. One approach I tried is

Greetings, I'm not on the list, so please CC me, thanks. :) Problem: printing a full-page graphic stops 3 inches into the print. System: FreeBSD 3.2 server running Samba 2.0.3 (version that is installed with the distribution) 486DX (4 or 8MB, I don't remember at the moment, I think 8.) 2 parallel ports Epson Color STYLUS 500 Epson Color STYLUS 800 Win95 client

Hello. Could you please help me solve the following LLC bug happening at instruction selection time: ISEL: Starting pattern match on root node: t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64 Initial Opcode index to 157 Skipped scope entry (due to false predicate) at index 162, continuing at 236 Match failed at

Hello, Tim, Thank you for your advice. Indeed, the problem with "LLVM ERROR: Cannot select" was a false predicate that should have been true. I solved the problem by simply making the C++ function implementing the TableGen predicate used in my store instruction (very similar to the selectIntAddrMSA predicate from the Mips back end) return true instead of false. But

Hello. I have problems specifying vector instructions with immediate values in TableGen. I wrote the following specification (I got inspired from the MSA vector instructions for the Mips back end): class MSA_I16_FMT<bits<9> opcode>: MSAInst { bits<16> s16; let Inst{31-23} = opcode; let Inst{26-11} = s16; }

I 100% get that we might not like the decisions clang-format is making, but how does one overcome this when adding new code? The pre-merge checks enforce clang-formatting before commit and that's a common review comment anyway for those who didn't join the pre-merge checking group. I'm just wondering are we not all following the same guidelines? Concerns of clang-format not being good

Hello. Does anybody have an idea why I'm getting the error below when using llc with arguments -O1 -disable-cgp? Note that this error is not given when using llc -O0. (I'd like to mention also I'm using custom Instruction selection for BUILD_VECTOR, which gets converted in my back end's machine instrution VLOAD_D, although the custom code seems to always select

Hi Liad, I'm not an expert in MC, but what you describe doesn't sound any different from how you would handle a branch instruction. Create an MCSymbol that represents the address of the target instruction; use that symbol as an operand in the referencing instruction; emit the symbol as a label just prior to emitting the target instruction. The second and third steps can occur in either

Hello. I'm writing a back end for a RISC processor (similar to BPF) with a large SIMD unit. I tried in the last days to make llc compile to SIMD code the following LLVM program: define i32 @foo(i32* %A, i32* %B, i32* %C, i32 %N) #0 { entry: ;vector.body: ; preds = %vector.body, %vector.body.preheader.split.split %0 = getelementptr inbounds i32, i32* %A, i64 0 ; i64 %index ; Alex: I

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure:

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -

Hey Paul, first of all thank you for taking the time to answer me, if I understand you correctly, I need to modify the instruction it self so one of it's operands is a symbol, and then at MC layer handle that symbol and add an entry to the symtab for that label? What kind of symbol should I use doing such thing? external symbol or MCSymbol? I was trying to find where in the code during the MC