similar to: attribute of intrinsic function

Displaying 20 results from an estimated 800 matches similar to: "attribute of intrinsic function"

2016 Mar 24
0
attribute of intrinsic function
> On Mar 24, 2016, at 12:45 PM, Xiangyang Guo via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > When I define an intrinsic function with memory write permission, my assumption is that we can either attach [IntrReadWriteArgMem] or [] to the intrinsic function. Based on the comment of the source code , "IntrReadWriteArgMem - This intrinsic reads and writes
2016 Mar 24
0
attribute of intrinsic function
On 03/24/2016 12:45 PM, Xiangyang Guo via llvm-dev wrote: > Hi, > > When I define an intrinsic function with memory write permission, my > assumption is that we can either attach [IntrReadWriteArgMem] or [] to > the intrinsic function. Based on the comment of the source code , > "IntrReadWriteArgMem - This intrinsic reads and writes only from > memory that one of its
2016 Mar 25
1
attribute of intrinsic function
Thanks for your reply, Philip. You are right, when I use LLVM-3.8, the 'argmemonly' shows up. Previously, I use LLVM-3.7. I think idempotent is what I want. Can you tell me how to add idempotent attribute to the function? Thanks. Regards, Xiangyang 2016-03-24 14:30 GMT-07:00 Philip Reames <listmail at philipreames.com>: > > > On 03/24/2016 12:45 PM, Xiangyang Guo via
2014 Jul 18
2
[LLVMdev] how to define INTRINSIC_W_CHAIN
sure! class TEST_INTINSIC_FM< string asmstr> : Intrinsic <llvm_i32_ty], [llvm_i32_ty, llvm_ptr_ty], [IntrReadWriteArgMem], !strconcat(“llvm.test”, asmstr),”.float”) >; tks On Jul 18, 2014, at 4:06 PM, Tom Stellard <tom at stellard.net> wrote: > On Fri, Jul 18, 2014 at 03:19:47PM -0400, kewuzhang wrote: >> en! >> >> my test is : %r1 =
2014 Jul 18
2
[LLVMdev] how to define INTRINSIC_W_CHAIN
Tks Tom, That is my confusing part. How can I make it to "access memory” so it will HasChain? Is there any flag set like in typeProfile, Node, instructions? myLoad, mayStore, SDNPHasChain? -kevin On Jul 18, 2014, at 4:26 PM, Tom Stellard <tom at stellard.net> wrote: > On Fri, Jul 18, 2014 at 04:15:45PM -0400, kewuzhang wrote: >> sure! >> >> class
2011 Aug 23
2
[LLVMdev] [RFC] Splitting init.trampoline into init.trampoline and adjust.trampoline
Hi! Attached set of patches splits llvm.init.trampoline into an "init" phase and an "adjust" phase, as discussed on the "Go on dragonegg" thread. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Split-intrinsics-and-DAG-nodes.patch Type: text/x-diff Size: 8808 bytes Desc:
2015 Jun 19
2
[LLVMdev] Attribute to mark that function only access memory through it's arguments
On 06/18/2015 09:15 PM, Nick Lewycky wrote: > > Currently in AliasAnalysis we can model ModRef behaviour for > functions which > only access memory through their pointer arguments. However we can't > express this propery as a function attribute. > > For example, for intrinsics we can specify ReadWriteArgMem or > ReadArgMem > attributes in
2014 Jul 18
2
[LLVMdev] how to define INTRINSIC_W_CHAIN
en! my test is : %r1 = call<float> @test.adddiv( <float> %r0, <float>* %p0). since >> but somehow it always fall into INTRINSIC_WO_CHAIN category. (caught it in lowering..) I think it doesn’t have chain in initial DAG. unfortunately the intrinsic “test.adddiv” is defined by me for now. not sure how to make it has a chain. kevin On Jul 18, 2014, at 3:06 PM,
2007 Jul 30
1
filenames
Dear all, I want to create filename from a loop, say, i=(1:10), and the final names will be file1.csv, file2.csv, file3.csv in Python, it seems easer as - "file"+str(i) +'.csv , but how can i do in R > list = as.character(1:10) > list [1] "1" "2" "3" "4" "5" "6" "7" "8" "9"
2007 Jun 07
2
[LLVMdev] How to call native functions from bytecode run in JIT?
Hello, can anyone help me calling native functions from LLVM-Bytecode functions run in the JIT? I have a program which creates an LLVM execution engine and adds modules and functions to it on the fly. I need to call some native functions of my program from bytecode functions which causes some troubles as it appears not to be documented. My test scenario works like the following: I have
2013 Aug 13
1
[Bug 843] New: ipset swap doesn't behave as expected
https://bugzilla.netfilter.org/show_bug.cgi?id=843 Summary: ipset swap doesn't behave as expected Product: ipset Version: unspecified Platform: All OS/Version: All Status: NEW Severity: minor Priority: P5 Component: default AssignedTo: netfilter-buglog at lists.netfilter.org ReportedBy:
2017 Feb 22
2
[Job Ad] Compiler Engineer positions at Intel
Hi, All, Our team within the Software and Services Group at Intel is looking for compiler engineers to join us. Currently two positions are available, see attached links. If you are interested, you can apply online or email me at xiangyang.guo at intel.com. Thanks. --Xiangyang (Mark) Guo
2019 Sep 03
2
Complex proposal v2
Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes: >> -----Original Message----- >> From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of David Greene >> via llvm-dev >> Sent: Thursday, August 29, 2019 10:05 AM >> To: llvm-dev <llvm-dev at lists.llvm.org> >> Subject: [EXT] [llvm-dev] Complex proposal v2 >>
2015 Apr 24
2
[LLVMdev] convert LLVM IR to another IR without SSA
Hi, Diego, Thanks for your quick reply. Inserting a copy instruction may not work here because I have a limitation of virtual register number. I need to assign registers with ssa form to registers without ssa form. I will look the source code you point out. Thanks Xiangyang On Fri, Apr 24, 2015 at 4:19 PM, Diego Novillo <dnovillo at google.com> wrote: > > > On Fri, Apr 24, 2015
2015 Dec 02
4
lower 64 bits constant
Hi, All, I want to lower 64 Bits constant such as 'long' and 'double'. So I define them like this: def CONSTI64 : InstFOO<(outs GRWideRegs:$dst), (ins i64imm:$src), "const-long $dst, $src", [(set (i64 GRWideRegs:$dst), imm:$src)]>{ let isMoveImm = 1; } def CONSTF64 : InstFOO<(outs
2015 Aug 21
2
loop unrolling introduces conditional branch
There's been some recent noise on the mailing list about requiring -fno-rtti; http://lists.llvm.org/pipermail/llvm-dev/2015-August/089010.html Could that be it? On Sat, Aug 22, 2015 at 12:21 AM, Xiangyang Guo via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, James and Philip, Thanks for your help. > > Based on your advice, I downloaded llvm-3.7. However, with this new
2015 Dec 01
2
LICM doesn't work for IntrReadMem intrinsic function
Thanks for your reply, escha, Yes, -loop-rorate makes it work. Regards, Xiangyang 2015-12-01 12:48 GMT-05:00 <escha at apple.com>: > > > On Dec 1, 2015, at 9:30 AM, Xiangyang Guo via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Hi, All, > > > > Suppose I define one memory read only intrinsic function "foo" in >
2007 Feb 05
0
[LLVMdev] automatically generating intrinsic declarations
On Mon, 5 Feb 2007, Dan Gohman wrote: > LLVM knows what all the types of the intrinsic functions are; I thought, > why are users (including llvm-gcc...) required to duplicate all this > information in order to use them? I mean in order to call > getOrInsertFunction to get declarations for them. That is an excellent question! :) In the bad old days, we used to allow intrinsics
2015 Dec 01
3
LICM doesn't work for IntrReadMem intrinsic function
On 1 December 2015 at 12:33, Xiangyang Guo via llvm-dev <llvm-dev at lists.llvm.org> wrote: > if I have the following IR, LICM doesn't work again, even if I use > '-loop-rotate' firstly. In this IR, the return value of intrinsic function > "foo" is used by another function "func2" as parameter. However, for the > intrinsic function
2016 Feb 03
2
TableGen register class
Hi, Assume I define registers R0...R15 and two register classes RegA and RegB. RegA contains R0 to R7 while RegB contains R0 to R15. Then I check the machine instruction, it seems that in some cases, the %vreg0 belongs to RegB; in other cases %vreg1 belongs to RegA_RegB. Can you tell me how TableGen decides which is which? At first, I guess &verg0 will be assigned by R8 to R15 only so that