similar to: testing of insert element instruction

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

I'm trying to figure out how to interpret DAG output that is shown below. If I were to draw it by hand, how would I do it? I tried to do it, but unfortunately I can't figure it out. I know there is a way to generate a graph, but I made some changes to my backend which hangs clang/llc. Would someone be kind enough to give a picture of what of a graph below? I'm sure once I see one I

> On Mar 18, 2016, at 12:52 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> >> On Mar 18, 2016, at 12:45 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote: >> >> On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote: >> On Thu,

> On Mar 18, 2016, at 1:37 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > >> I think you created a cycle, this is easy to do with SelectionDAG :) >> Basically SelecitonDAG will iterate until it does not see anything to change. So if you insert a transformation on a pattern A, that generates pattern B, while you have another transformation that matches B and

On Tue, Mar 15, 2016 at 2:21 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 3/15/2016 4:16 PM, Rail Shafigulin via llvm-dev wrote: > >> Below is the output of llc with a -debug-only=isel. As you could see the >> output type for load, store, and add changes from v4i32 to i32 during >> legalization. How can I preserve the output type to

i'm getting a Could not infer all types in pattern! error in my backend. it is happening on the following instruction: VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32} VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)). how do i make it use appropriate types? in other words if it is f32 then use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start? any help is appreciated.

Hi Chandler, While doing the performance measurement on a Ivy Bridge, I ran into compile time errors. I saw a bunch of “cannot select" in the LLVM test suite with -march=core-avx-i. E.g., SingleSource/UnitTests/Vector/SSE/sse.isamax.c is failing at O3 -march=core-avx-i with: fatal error: error in backend: Cannot select: 0x7f91b99a6420: v4i32 = bitcast 0x7f91b99b0e10 [ORD=3] [ID=27]

On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> Hi Rail, >> >> Two hints to begin with: >> >> 1) Makes sure you example is

I've run into a situation in isel where it seems like the selector is generating a cycle in the DAG. I have something like this: 0x215f140: v2f64 = llvm.x86.sse2.min.sd 0x215efd0, 0x21606d0, 0x215eb80 [0] 0x215efd0: i64 = Constant <647> [0] 0x21606d0: v2f64 = scalar_to_vector 0x213b8f0 [0] 0x213b8f0: f64,ch = load 0x213b780, 0x213aa90, 0x213b610 <0x2113690:0> alignment=8

On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > Hi Rail, > > Two hints to begin with: > > 1) Makes sure you example is vectorized on X86 for example > 2) Is your target correctly overriding the TTI (declaring the vector > register size for example) so that the vectorizer can kicks-in (see > X86TTIImpl::getRegisterBitWidth for

My question is: How do I make clang to generate assembly with vector instruction for my target? The back story is: I've added a few vector instructions to my target and confirmed that they are used by running my code on the test below and using a following command: opt i.esencia.ll -S -march=esencia -mcpu=esencia -loop-vectorize | llc -mcpu=esencia -o i.esencia.s target datalayout =

I've run the SingleSource test suite for core-avx-i and have no failures here so a preprocessed file + commandline would be very useful if this reproduces for you still. On Sat, Sep 6, 2014 at 4:07 PM, Chandler Carruth <chandlerc at gmail.com> wrote: > I'm having trouble reproducing this. I'm trying to get LNT to actually > run, but manually compiling the given source

i'm having difficulty in understanding the BUILD_VECTOR instruction and how to lower it to the an actual ISA. i looked at other targets but wasn't quite able to figure it out. would someone be able to dumb it down for me? assume i have an insert element instruction which inserts an element from a GPR to a Vector Register at a given index, i..e vset <vector register> <gpr>

I have added new instructions to my target, unfortunately they are not being properly type legalized. The instructions I've added are a vector add, vector load and a vector store. Can anyone lend a hand on how to legalize them so that my target would be able to recognize them. Below is the output of llc with a -debug-only=isel. As you could see the output type for load, store, and add changes

On Thu, Feb 18, 2016 at 11:22 AM, Jonathan Roelofs < jonathan at codesourcery.com> wrote: > > > On 2/18/16 12:19 PM, Rail Shafigulin via llvm-dev wrote: > >> >> >> On Thu, Feb 18, 2016 at 10:50 AM, Krzysztof Parzyszek via llvm-dev >> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> On 2/18/2016

I am wondering if there is a good/easy way to recover the original type of a pointer parameter in the SDAG. Here's the problem that I am dealing with: define <4 x i32> @test(i32* nocapture readonly %a) local_unnamed_addr #0 { entry: %0 = bitcast i32* %a to <4 x i32>* %1 = load <4 x i32>, <4 x i32>* %0, align 16, !tbaa !2 ret <4 x i32> %1 } The problem is

> On Sep 7, 2014, at 8:49 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > Sure, > > Here is the command line: > clang -cc1 -triple x86_64-apple-macosx -S -disable-free -disable-llvm-verifier -main-file-name tmp.i -mrelocation-model pic -pic-level 2 -mdisable-fp-elim -masm-verbose -munwind-tables -target-cpu core-avx-i -O3 -ferror-limit 19 -fmessage-length 114

On Thu, Feb 18, 2016 at 11:48 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:40 PM, Rail Shafigulin wrote: > >> >> 0x3283608: i32,ch = CopyFromReg 0x3257980, 0x3283500 [ORD=1] >> [ID=9] >> 0x3283500: i32 = Register %vreg5 [ID=1] >> >> Based on the code above, CopyFromReg is a node at

On 26 Dec 2016, at 14:58, Nemanja Ivanovic via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I am wondering if there is a good/easy way to recover the original type of a pointer parameter in the SDAG. Here's the problem that I am dealing with: > > define <4 x i32> @test(i32* nocapture readonly %a) local_unnamed_addr #0 { > entry: > %0 = bitcast i32* %a to

On Thu, Feb 18, 2016 at 11:34 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 2/18/2016 1:32 PM, Rail Shafigulin wrote: > >> I think this is where I'm loosing the "thread". Based on what I'm seeing >> SET_FLAG has three operands, the first of which is a CopyFromReg. So how >> come the pattern is SET_FLAG %vreg5, 3, 20 and not