similar to: [LLVMdev] Wrong encoding/decoding for POPC instruction of Sparc

I'll look into it, thanks for the report. On Thu, Jul 30, 2015 at 11:01 PM, Jun Koi <junkoi2004 at gmail.com> wrote: > Any ideas on this bug? > > Thanks. > > > On Wed, Jul 29, 2015 at 12:17 AM, Jun Koi <junkoi2004 at gmail.com> wrote: > >> Hello, >> >> There is an issue in the latest Sparc code: while we can encode POPC, >> decode

Any ideas on this bug? Thanks. On Wed, Jul 29, 2015 at 12:17 AM, Jun Koi <junkoi2004 at gmail.com> wrote: > Hello, > > There is an issue in the latest Sparc code: while we can encode POPC, > decode results in crash in llvm-mc > > $ echo "popc %g1, %g2" | ./Release+Asserts/bin/llvm-mc -assemble > -triple=sparcv9 -show-encoding > .text > popc

Hi James, Not sure if you've already found the problem but I've been looking at this issue a bit as a way to learn. What I've seen is that the wrong operand names are used for the instruction which causes the decoder emitter to fail to recognize the operands. The attached patch changes the names of the operands and adds a test for the disassembly of the instruction. I haven't

> > but doesn't emit optnone and nounwind attributes > s/nounwind/noinline On Mon, Jan 28, 2019 at 11:35 AM Jakub (Kuba) Kuderski < kubakuderski at gmail.com> wrote: > As far as I understand, gllvm doesn't run LTO pipeline or any cross-module > optimization, and the optimization level provided is only used to compile > each Translation Unit separately. > If you

Hello all, I have two matrices, pop and pop2, each the same number of rows and columns that I want to compare for equality. I am concerned about efficiency in this operation. I've tried a few things without success so far. Doing something simple like: if (pop==pop2) { cat('equal') } else { cat('NOT equal') } results in the warning: 1: In if (pop == pop2) { : the

Hello, While trying to find out why the LDC compiler refuses to generate object code for MSP430 targets (but generates MSP430 assembly or LLVM IR/bitcode), I came across the following apparent inconsistency. This works: $ clang --target=msp430 -c test.c This doesn't work: $ clang --target=msp430 -S -emit-llvm test.c $ llc -filetype=obj test.ll /opt/msp430/bin/llc: target does not support

Jim, You are correct: MipsSubtarget. For llvm-mc we have a straight MCSubtargetInfo object. For llc we get a MipsSubtarget object which derives from MipsGenSubtargetInfo which derives from TargetSubtargetInfo which derives from MCSubtargetInfo. The patch I hope to send out for review will do this: Add a new data member to MCSubtargetInfo base class. It will be a set of integers that is used or

On Dec 10, 2012, at 1:15 PM, "Carter, Jack" <jcarter at mips.com> wrote: > Here are some examples using the gnu assembler reacting to the same input file with different commandline options. > > These are using the GCC assembler on hello.c > // abi o32, arch mips32r2, relocation model pic+cpic > mips-linux-gnu-as -mips32r2 -EL -KPIC -o hello_gas.o hello_gas.s >

Thanks, Alex. See my comments below. On Wed, Aug 23, 2017 at 12:59 AM, Alex Bradbury <asb at asbradbury.org> wrote: > On 22 August 2017 at 23:39, Y Song via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> Hi, > > Hi Yonghong. > >> I found some different discrepancy on how Subtarget is created >> between some arch specific TargetMachine constructor.

Does LLVM 8 work in macOS 10.9.5? -- Mark

Here are some examples using the gnu assembler reacting to the same input file with different commandline options. These are using the GCC assembler on hello.c // abi o32, arch mips32r2, relocation model pic+cpic mips-linux-gnu-as -mips32r2 -EL -KPIC -o hello_gas.o hello_gas.s e_flags 0x70001007 EF_MIPS_NOREORDER EF_MIPS_PIC EF_MIPS_CPIC E_MIPS_ABI_O32 EF_MIPS_ARCH_32R2 // abi

Hi Bradley, I was doing some performance analysis for ARMv7 (cortex-a9) and I noticed that one of my benchmarks degraded by 93%. I have tracked the regression down to the following commit by you: / //commit 7c1b77248baaeafec5d6433c3d1da9a2e2b69595// //Author: Bradley Smith <bradley.smith at arm.com>// //Date: Mon Nov 16 11:10:19 2015 +0000// // [ARM] Introduce subtarget features per

In a pass I’m working on, I’ve done some manipulation of several functions, replacing them with new copies with different types, etc. The LLVM IR passes the verifier, but when I have debug symbols enabled (“-g”), I get the following error when Clang generates the Dwarf info (using a very recent build of LLVM/Clang from Git mirror): > Assertion failed: (TheCU && "Unable to find

i want to emit binary code for the following implemented vector assembly instructions. P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b] P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c] P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0 P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0 I added the following lines in X86MCInstLower.cpp; unsigned NewOpc; switch (OutMI.getOpcode())

Hello all, I have written a pass, which replaces condition branchinst using indirectBr to obfuscate program. The origin IR is as the following: br i1 %1, label %2, label %3 And the transformed IR is as the follwoing: %4 = select i1 %1, i8* blockaddress(@func, %2), i8* blockaddress(@func, %3) indirectbr i8* %4, [label %2, label %3] The pass's core function is as the

Hello, while invoking opt with all possible optimization pairs I stumbled over a stack dump when doing -early-cse-memssa twice: $ clang -Xclang -disable-O0-optnone -S -o fannkuch7.ll -emit-llvm fannkuch7.c $ opt -S -o fannkuch7.ll -early-cse-memssa -early-cse-memssa fannkuch7.ll Questions: Is it illegal to call -early-cse-memssa twice? Are there any other incompatible optimization orders?

Ah ha! I found crash reports: green-dragon-03:DiagnosticReports buildslave$ cat mmap_stress.cc.tmp_2016-01-19-231335_green-dragon-03.crash Process: mmap_stress.cc.tmp [95010] Path: /Users/USER/*/mmap_stress.cc.tmp Identifier: mmap_stress.cc.tmp Version: 0 Code Type: X86-64 (Native) Parent Process: bash [95004] User ID:

Tim, How about the below option ? 1. Specify an existing generic armv7 CPU or the CPU which is close my custom variant. My custom variant can be treated as "cortex-a9" + hwdiv. So my CPU here is "cortex-a9" 2. Specify the ".arch_extension idiv" which is available as an extension for my custom variant. 3. Teach LLVM & Clang about your CPU's

Hi, I found some different discrepancy on how Subtarget is created between some arch specific TargetMachine constructor. For example, for BPF/Lanai: BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options,

Hello everyone, I'm a newbie of llvm. I'm trying to insert Intel MPX instruction BNDCU with BuildMI. I add my machinefunctionpass at addPreEmitPass2. Here is the code of insertion: BuildMI(MBB, MI, DL, TII->get(X86::BNDCU64rr)).addReg(X86::BND2, RegState::Define).addReg(X86::R10); And here is to stack track when I compiler program with modified llc: