similar to: [LLVMdev] [ARM backend] adding pattern for SMLALBB

Hello, I built a llvm toolchain for ARM and I'm trying to build a simple application on ARM using LLVM. When I compiled the code, it has the following message and the binary code has a segmentation fault when it is executed. /tmp/ccJPjMe4.s: Assembler messages: /tmp/ccJPjMe4.s:4250: rdhi, rdlo and rm must all be different /tmp/ccJPjMe4.s:4589: rdhi, rdlo and rm must all be different

On Jul 8, 2009, at 11:04 AMPDT, Won J Jeon wrote: > Hello, > > I built a llvm toolchain for ARM and I'm trying to build a simple > application on ARM using LLVM. When I compiled the code, it has the > following message and the binary code has a segmentation fault when > it is executed. > > /tmp/ccJPjMe4.s: Assembler messages: > /tmp/ccJPjMe4.s:4250: rdhi, rdlo

I tried a couple of options (-mcpu=arm1136j-s, -mcpu=arm1136jf-s, -march=armv6, ...) to let the compile know the specific ARM processor, but the same issue is still there. I tried to take a look at .s file in /tmp directory, but it's already cleaned up. Is it because I enabled the optimization option when I compiled llvm? Regards, Won On Wed, Jul 8, 2009 at 1:28 PM, Dale Johannesen <dalej

On Jul 8, 2009, at 12:52 PMPDT, Won J Jeon wrote: > I tried a couple of options (-mcpu=arm1136j-s, -mcpu=arm1136jf-s, - > march=armv6, ...) to let the compile know the specific ARM > processor, but the same issue is still there. I tried to take a look > at .s file in /tmp directory, but it's already cleaned up. Is it > because I enabled the optimization option when I

Thanks. I could take a look at the lines and all of them have smull instruction like 'smull r0, r1, r0, r1'. Won On Wed, Jul 8, 2009 at 2:54 PM, Dale Johannesen <dalej at apple.com> wrote: > > On Jul 8, 2009, at 12:52 PMPDT, Won J Jeon wrote: > > I tried a couple of options (-mcpu=arm1136j-s, -mcpu=arm1136jf-s, > -march=armv6, ...) to let the compile know the

Hello > /tmp/cczBL31y.s:409: rdhi, rdlo and rm must all be different This is binutils bug fixed ~2 years ago: http://sourceware.org/ml/binutils/2007-11/msg00046.html Make sure you're using the latest binutils for ARM (from binutils CVS) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

This is the full description of errors I am getting /home/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/xgcc -B/home/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/ -B/usr/local/armv7fl-montavista-linux-gnueabi/bin/ -B/usr/local/armv7fl-montavista-linux-gnueabi/lib/ -isystem /usr/local/armv7fl-montavista-linux-gnueabi/include -isystem

Hello, Thanks for the reply. We have an product whose one part has lot of algorithms doing some graphics work. Our intention was to figure out if there can be any performance gain if we use llvm instead of native ARM. This is for ARM target. Earlier, I have built this component using llvm and tested it on x86. Performance was 4x as compared to native gcc. Then I built llvm for ARM and tested

Hi, guys I am interesting about how to get the switch case value form the Machine Instruction. I know the switch will be converted to jump-table in the Machine Instruction. And in the phase CodeGen , the case-value of SwitchInst can get esasly. but it seems no case -value in Machine Instruction. The MI as follows: Frame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4,

Hi, all I am trying to selfhost LLVM and Clanf on ARM. Hopefully doing this can reveal what version of GCC is broken. But I have a concern about the following message while building LLVM and Clang by using clang (selfhost build). --- llvm[1]: Compiling DeltaAlgorithm.cpp for Debug build /tmp/cc-DqWGS1.s: Assembler messages: /tmp/cc-DqWGS1.s:8963: Rd and Rm should be different in mul llvm[1]:

Some glitch in the emailer? I have received this message 3 times in a row!? I think that by the time it gets as far as MI-level there is no reversible method of determining the 'case' label at all. The reason I say this, is that I have often seen optimisations that coalesce groups of values into interesting logical tests and jump-tables are completely avoided. For example, a simple

Thanks for your help. Is there possible I can get the realily case value form the MI? For the case in https://bugs.llvm.org/show_bug.cgi?id=34902. as follows. ############################# * GCC v7.1 generated assembly ############################# ** Options: -Os -marm -march=armv7-a foo: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 sub

Hi, Any help would b appreicated. This is one of my critical assignment. Thanks Sanjeev On Thu, Jun 17, 2010 at 7:03 PM, Sanjeev chugh <sanjuchugh at gmail.com> wrote: > Hello, > > Thanks for the reply. We have an product whose one part has lot of > algorithms doing some graphics work. Our intention was to figure out if > there can be any performance gain if we use llvm

Hi Micah, You can just create a new register class that only contains the registers you want and use that for the instruction. The set theoretic operators for register class definition make this very easy. See the ARM backend definitions of GPRnopc, rGPR, etc.. for examples. -Jim On Aug 16, 2011, at 9:18 AM, Villmow, Micah wrote: > Is there a way in tablegen to specify that a certain

On Nov 23, 2015, at 12:04 PM, John Ridges <jridges at masque.com<mailto:jridges at masque.com>> wrote: Hi Jonathan. I really, really hate to bring this up this late in the game, but I just noticed that your NEON code doesn't use any of the "high" intrinsics for ARM64, e.g. instead of: int32x4_t coef1 = vmovl_s16(vget_high_s16(coef16)); you could use: int32x4_t coef1

Jim, Thanks for the hints. Does LLVM allow allocation of the same register across register classes? For example, in the ARM backend, can an instruction write to R0 when it is part of register class tGPR, but then use R0 in the next instruction as a source register from the rGPR class? If LLVM can do this, then this will work. Micah > -----Original Message----- > From: Jim Grosbach

Hi, guys I am interesting about how to get the switch case value form the Machine Instruction. I know the switch will be converted to jump-table in the Machine Instruction. And in the phase CodeGen , the case-value of SwitchInst can get esasly. but it seems no case -value in Machine Instruction. The MI as follows: Frame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4,

On 2010-06-04 13:41, Sanjeev C wrote: > I get following errors: > > /home/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/xgcc > -B/home/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/ > -B/usr/local/armv7fl-montavista-linux-gnueabi/bin/ > -B/usr/local/armv7fl-montavista-linux-gnueabi/lib/ -isystem > /usr/local/armv7fl-montavista-linux-gnueabi/include -isystem >

Is there a way in tablegen to specify that a certain instruction can only be allocated with a certain subset of a register class? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110816/329bea6e/attachment.html>

I'm getting following errors while cross compiling llvm for ARM. Please help since it is urgent and critical My gcc version is 4.2.0, 32bit Linux and target is ARM Configure options are: ./configure --host=i686-pc-linux-gnu --build=i686-pc-linux-gnu --target=armv7fl-montavista-linux-gnueabi --enable-cross --with-sysroot=/home//arm_v7_vfp_le/target/