similar to: [LLVMdev] RFC: Separate machine IR from lib/CodeGen into lib/MIR

> On May 26, 2015, at 1:37 PM, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > >> >> On 2015-May-26, at 09:46, Alex L <arphaman at gmail.com> wrote: >> >> Hi all, >> >> The CodeGen library is a big bag of interdependent bits. This caused >> a circular dependency in the MIR serialization commit (r237954), which got >>

+1. Could those two be subdirectories of one “Machine-Related-Stuff” directory? E.g., MachineStuff/IR MachineStuff/CodeGen Where MachineStuff is something meaningful :). That way, they keep a logic bound, more formal than the naming convention. My 2c. Q. > On May 26, 2015, at 9:28 PM, Chris Lattner <clattner at apple.com> wrote: > > On May 26, 2015, at 1:46 PM, Owen Anderson

Dear LLVM developers, My goal is to write LLVM Machine IR (MIR) passes to analyze the assembly source code. But it seems I need to find a way to translate the handwritten assembly code into MIR format first. Is there any materials, or any modules in LLVM source code, that can help to translate assembly code into LLVM MIR for analysis? Or is there any easier ways to analyze assembly code in MIR

Hello Valentin, To generate a mir test case i think the process is to first create an IR file by passing '-S -emit-llvm' to clang, then you can feed that file into llc and use stop-before to get the mir just before the if-converter pass, eg: `llc -stop-before=if-converter -simplify-mir -o test.mir test.ll`. Also there is a MIR language reference: https://llvm.org/docs/MIRLangRef.html

Hello, I am trying to isolate an assertion failure in if-converter (on PPC) and I generated a textual debuglog with: ``` LLVM_ARGS=-print-before-all -print-module-scope -filter-print-funcs=japi1__require_7687 ``` and after splicing out the the MIR before the if-converter pass I would like to run `llc -march=ppc64le -run-pass=if-converter input.mir` so that I can start minimising the MIR. This

In light (pun not intended) of the announcement here https://wiki.ubuntu.com/MirSpec what does this mean for LightDM being a viable free desktop display manager. The diagram shows the system compositor as being launched by LightDM in much the same way X is, and the plan looks very much like what we would do for Wayland. Is MIR going to be a hard dependency? Is Wayland support going to be dropped

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

Llvm-mctoll will raise a binary back to LLVM IR. Not exactly what you want but it might be something you can leverage. https://github.com/microsoft/llvm-mctoll On Mon, Nov 25, 2019 at 1:19 PM Nicolai Hähnle via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On Thu, Nov 21, 2019 at 3:37 AM Lele Ma via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > My goal is to write

Thank you both! I was running into the issue that bugpoint was reducing my test-case into other failures and I hadn't managed yet to find the right point in the Julia pass pipeline to insert the module to reproduce the issue reliably from llc and that's why I started looking at using the MIR. I will go back at looking at the pass pipeline and the IR and get a reproducer that way!

Valentin, in terms of limitations as Sean pointed out, an important one is that .mir doesn't have MachineFunctionInfo which may result in failure on accesses to global variables due to use of register X2. The verifier considers it an undefined register. Also, it's probably easier to reduce test cases using bugpoint starting from an IR test case. With the code you provided, I get a

I am confused about the rules for when upper and lower case letters should be used in MIR. As an example our downstream target has upper case letters in its sub-register indices and as a result we cannot import exported MIR without manually 'lower casing' it first which is obviously rather annoying. Looking in https://llvm.org/docs/MIRLangRef.html it is stated that instruction names are

Hi A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are reserved for vregs. We've decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil

Can we use %% for vregs? Seems slightly easier to remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at

Hi all, After a recent upstream merge into our downstream sources we are suddenly encountering the freeze instruction in LLVM IR for div/rem pairs. This seems to be related to [1]. Our downstream target is GlobalISel only and unfortunately GlobalISel doesn't support this instruction yet, so most of our internal test-suite is now breaking due to GlobalISel not being able to translate this

On Mon, Jan 8, 2018 at 2:27 PM, Matthias Braun <mbraun at apple.com> wrote: > When we discussed this our line of thought was like this: > > - LLVM IR already uses %name for SSA values which is closer to what a vreg > is than to what a physreg is. It would be neat to draw that parallel to > llvm IR. > - We wanted another sigil for physregs so they are easy to differentiate

Hi, I noticed that a while ago the isSSA flag was removed from MIR, and this property is now computed. However, the deduction only checks the virtual registers (whether they are assigned to more than once). Now I have MIR tests which live after RA, so they only contain physical registers, so the parser determines they are in SSA form. These tests now fail because some of our passes can be

The MIR format currently has a short-hand syntax for declaring vreg classes and banks in the function body so you can write something like this: name: foo body: | %3:gpr(s64) = ... rather than the much more verbose and awkward: name: foo registers: - { id: 3, class: gpr } body: | %3(s64) = ... I'd like to make this shorthand the only way to do this. There are a few

When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of

In our fork of LLVM we often need to reduce a crash testcase for a specific assertion. After writing lots of "only give me this specific assertion" scripts like the above I decided to write a script that automates all this for me: <https://github.com/CTSRD-CHERI/clang/blob/master/utils/creduce_crash_testcase.py>. (It's called creduce_crash_test.py but it will actually use

I'm not sure if this helps, but here it is in case it does. I typically use bugpoint in a way as to keep the actual failure that I'm after. For example, with the test case you've pasted, I was looking for a specific assert. So I used bugpoint this way: $ cat reduceme.sh #!/bin/bash llc -filetype=obj $1 2>&1 | grep 'Cannot lower calls with arbitrary operand bundles'