similar to: [LLVMdev] Support for bundles of MCInst?

Mario, On Nov 29, 2012, at 3:00 PM, Mario Guerra <mariog at codeaurora.org> wrote: > We're developing an integrated assembler for a VLIW target, and some of the > optimizing our assembler needs to do must be done on a per-packet basis. > This requires us to be able to traverse instruction within a packet, and one > particular optimization requires traversal of previous

Hello Owen, > There should already be sufficient support for what you're trying to do. See > MCOperand::CreateInst(). The concept is that you'll build a composite MCInst in > your AsmPrinter::EmitInstruction() method, which uses Inst-type MCOperands to > hold a list of sub-instructions. Then you call AsmStreamer::EmitInstruction() on the > composite MCInst. Thanks for

Mario, On Nov 29, 2012, at 4:04 PM, Mario Guerra <mariog at codeaurora.org> wrote: > Thanks for your reply. This is actually one approach we are considering, but > there are a few issues with it we weren't sure how to address. > > One is that the lifespan of an MCInst seems to be limited to the scope of > AsmPrinter, and we need them to be persistent in order to do a

On Thu, Nov 29, 2012 at 3:00 PM, Mario Guerra <mariog at codeaurora.org> wrote: > Hello all, > > We're developing an integrated assembler for a VLIW target, and some of the > optimizing our assembler needs to do must be done on a per-packet basis. > This requires us to be able to traverse instruction within a packet, and one > particular optimization requires traversal

Can someone explain what MCInst is vs. MachineIntr? I'm porting some patches we have here that affect MachineInstrs and am wondering whether I need to make similar changes in MCInst. Why do we have two machine instruction representations? -Dave

Hello everyone, I'm a newbie of llvm. I'm trying to insert Intel MPX instruction BNDCU with BuildMI. I add my machinefunctionpass at addPreEmitPass2. Here is the code of insertion: BuildMI(MBB, MI, DL, TII->get(X86::BNDCU64rr)).addReg(X86::BND2, RegState::Define).addReg(X86::R10); And here is to stack track when I compiler program with modified llc:

Hi all. I'm looking for some way to do code analysis with LLVM. Can someone please give me a hint, if it is possible to query an MCInst for what are input operands and what are output operands? Small example. Consider we have an instruction: str r1, [sp, #8] Being mapped into MCInst instance it has the following operands: <MCOperand Reg:61> <-- maps to reg r1

llvm-dev, Thanks so much in advance for any help, tips, or advice you may be able to offer me. I'm going to try to avoid the big-picture description of the project I'm working on, and only talk about the parts that I have trouble with / currently need to implement. -- I've been starting by taking the source code from the "llvm-mc" tool, and working that down into a

A question for LLVM code generator developers: After having read through "The LLVM Target-Independent Code Generator" [1] I'm unclear about what precisely the objects MCInst and MCOperand represent. They sit in the space between assembly syntax and binary encodings, but which are they modeling? For example, a Thumb 2 branch instruction 'b' takes an immediate. That syntax

On Jul 9, 2009, at 5:34 PM, David Greene wrote: > Can someone explain what MCInst is vs. MachineIntr? Sure. MCInst is designed to be part of the "MC" set of libraries, which is stuff dealing with machine code. We're building a suite of assemblers and disassemblers out of this. MCInst is integral to this plan. For an assembler you have two pieces: 1. "Recognize"

GCC-style inline assembly is notoriously hard to write correctly, because it is the user's responsibility to tell the compiler about the requirements of the assembly (inputs, output, modified registers, memory access), and getting this wrong results in silently generating incorrect code. This is also dependent on register allocation and scheduling decisions made by the compiler, so an inline

Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 

Hi folks, I'm looking for a developer to join my team in Austin to help develop linker back ends for ARM and AArch64. Given that this is the LLVM dev list, I want to be clear that the work involves close collaboration with our internal LLVM teams so LLVM experience is a definite plus, but it does not involve direct development on LLVM. I'm ideally looking for someone with direct

Hi, In GCC there is one useful option -dp (or -dP for more verbose output) to annotate assembler with instruction patterns, that was used when assembler was generated. For example: double test(long long s) { return s; } gcc -S -dp -O0 test.c test: .LFB0: .cfi_startproc pushq %rbp # 18 *pushdi2_rex64/1 [length = 1] .cfi_def_cfa_offset 16 movq %rsp, %rbp # 19 *movdi_1_rex64/2

Hello everyone, In the file *lib/CodeGen/AsmPrinter/AsmPrinter.cpp*, I would like to obtain an MCInst corresponding to its MachineInstr. Can anyone tell me a way to do that? If that is not possible, then, I would like to know if a given MachineInstr is an *lea *instruction and I would like to know if the symbol involved with this lea instruction is a jump-table. For instance, given a

Owen is correct in his descriptions. The MCOperand values are intended to model the instruction encoding. Where that doesn't match the assembly syntax, the asm parser (and codegen) and the instruction printer are responsible for encoding/decoding the values. For targets that predate the MC layer, this isn't always the case, leading to things being a bit confusing when just reading the

On 02.03.2012, at 09:20, Konstantin Vladimirov wrote: > Hi, > > In GCC there is one useful option -dp (or -dP for more verbose output) > to annotate assembler with instruction patterns, that was used when > assembler was generated. For example: The internal "-mllvm -show-mc-inst" option is probably as close as you can get. $ clang -S -O0 test.c -mllvm -show-mc-inst -o

Dear All, I am following a flow to generate object files(.o) from input (.s assembly) files. The input .s is given to AsmParser, which creates MCInst after matching instruction opcode. These MCInst are converted to MCStream and then finally emitting to an object file using Target Code Emitter. I am considering whether hazard recognition can be done on the list of MCInst, which I get after

Owen, On 11/29/12 18:16, Owen Anderson wrote: >> Will the size of the >> packet be properly accounted for by the MCObjectStreamer if we have to pad >> the packet (mainly for fetch alignment)? > The MC system (including relaxation) is capable of handling instructions with variable length encodings whose size can't be determined until the MCCodeEmitter step. Where could I

The MCInstrDesc has a method getNumDefs() which tells you how many 'out registers' that MCInst has. The 'out' registers are always at the beginning of the list. You can also use getNumOperands(). Not sure if this is what you are looking for. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Vladimir Pouzanov