similar to: New TableGen backend for debugging

I'm glad you find it useful. I haven't thought about it being done as part of the build, nor am I any sort of build guru. What do other people think? At 10/7/2020 08:12 AM, Nemanja Ivanovic wrote: >This is really useful. Is there a way to produce this output automatically (by providing some CMake variable)? For example, something like: >-DBUILD_TBLGEN_DEBUG=<Target> >

This is the second in a series of occasional TableGen newsletters. The purpose is to inform the greater LLVM community of changes and enhancements to TableGen and its backends. * As announced previously, there are two new TableGen documents and three updated ones: TableGen Overview --- https://llvm.org/docs/TableGen/ TableGen Programmer's Reference ---

Are all the records collected as they are parsed, with template parameter substitution and lets, and *then*, after all records are collected, a "pass" is made to calculate the inter-field expressions? Once I understand this, I will add a section to the new guide to explain it. I presume it is the case that this behavior should be publicized. It also appears to be the case that a record

I had another idea for a TableGen tracing feature and would like some feedback. It's quite possible I'm on the wrong track here and that improved backend tracing is what folks really need. The idea is to add a -trace option to the tblgen command line. With it you can list one or more record names. TableGen would produce a detailed trace of how the record is built: class inheritances,

I hacked around a bit with the simple case of tracing just classes and defs (no multiclasses or defms). Below you will see my test file and then the output produced. Note that the regular output from the PrintRecords backend follows the trace, so you can see the final classes and records there. Once the trace can be selective, it makes sense to add another option for PrintRecords that restricts

Yes, I understand the problem. To be more useful, TableGen would have to carry the traces along with the classes and records and (re)display the values while the substitutions are being made. I'm writing a new Programmer's Guide for TableGen and have been digging into the parse-time versus substitution-time issue. I haven't found a document that makes it clear. Can you give a quick

Jakob Stoklund Olesen <jolesen at apple.com> writes: > The TableGen language seems to be growing Lisp macros from two > different directions. > > Che-Liang Chiou added a preprocessor with for loops, and David Greene > added multidefs. > > It seems that some kind of macro facility is needed, perhaps we should > discuss what it is supposed to look like? Don't

A question for all you TableGen aficionados: Does anyone know why the collection of RecordVal field values stored in a Record are represented by a SmallVector rather than some sort of map? This means that every time a record field is looked up by name, a linear search is performed. Is it a question of RAM usage?

I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace =

Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate? -Owen On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I am trying to make

Thank you for the work here.  This is awesome to see. Philip On 11/16/20 12:30 PM, Paul C. Anagnostopoulos via llvm-dev wrote: > This is the second in a series of occasional TableGen newsletters. The > purpose is to inform the greater LLVM community of changes and enhancements > to TableGen and its backends. > > * As announced previously, there are two new TableGen documents and

Are you talking about the type checking done in CodeGenDAGPatterns.cpp? Is it easy to post an example? At 11/18/2020 01:55 PM, Thomas Lively wrote: >Hi Paul, > >I think this would be time well spent. At least in the WebAssembly backend, the vast majority of our ISel work is still done with DAG ISel. I know this is different from the performance work you have in mind, but one of my

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat for 15

I've got another idea for a tblgen extension but I don't have a good feel for how feasible it is. Hopefully someone can provide guidance. What I want to do is something like this: class C1<int A, string B> { int foo = A; string bar = B; } class Bb<int A> : C1<A, "foo">; class Cb<int A> : C1<A, "bar">; class C2<C1 Base, int

I have been reading the “RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends” topic with considerable interest. This is an approach I have been considering for taming our own large instruction set, and it looks like it structures our descriptions better than the conventional approach we have used so far. However, I have another form of TableGen taming that I

Hi Paul, If all you care about is debugging then for now we can just emit a few more debug messages which would help to "trace" the flow. To distinguish traces you can prefix it with some known string. I don't think you really need a 'trace' tag in the language spec for this. Debugging Tablegen has always been a nightmare and I don't think we can ever reach a stage where

>From my understanding, NAME is a special builtin entry and dedicated for things related multiclass, So, is the following rewrite what you want? class Base<int V> { int Value = V; } class Derived<string Truth> : Base<!if(!eq(Truth, "true"), 1, 0)>; multiclass Derived_m<string T> { def #NAME# : Derived<T>; } defm TRUE :

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.

I believe multiclasses can be nested. Could that help you reduce the duplication? --Sean Silva On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: > > multiclass