similar to: My first real submission with Phabricator

Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org>於 2020年8月9日 週日，上午1:53寫道： > Hi Paul, > I hope you have gone through > https://llvm.org/docs/Contributing.html#how-to-submit-a-patch. > > Generally, I would do 'git add' on the new file. 'git diff' should show me > the newly added file. Further, I'd just do 'arc diff' and this should

Well, I was hinting at LLVM_DEBUG messages. You can pretty much dump all "actions" Tablegen would take to process a .td file, which should suffice, IMO. On Wed, Aug 5, 2020 at 5:59 PM Paul C. Anagnostopoulos <paul at windfall.com> wrote: > Your reply suggests that there is a way to see debug messages from > TableGen. Is that what you meant? If so, can you explain how that

On Tue, Oct 13, 2020 at 10:47 AM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote: > What do you guys think about the below enhancements? > > 5. !getdagrestype(dag [, index]) - Returns type of result value. If the DAG computes multiple values then return type of 'index'th result. > > 6. !setdagrestype(dag target_dag, type T [, index]) - Set return type of

I understood that the name is a matching tag for the operand and not its name (as in named macro or function arguments). However, I was assuming that the names in any one DAG node had to be unique and so could serve as selectors for operands. But a quick investigation shows that I was wrong: names can be duplicated in the same node. So DAG indexes are integers only. At 10/12/2020 01:46 PM,

Hi Paul, If all you care about is debugging then for now we can just emit a few more debug messages which would help to "trace" the flow. To distinguish traces you can prefix it with some known string. I don't think you really need a 'trace' tag in the language spec for this. Debugging Tablegen has always been a nightmare and I don't think we can ever reach a stage where

John, I'm pretty much down to details and smoothing the text. Here is a pdf. Can you mark it with comments? Or you can send an email with a list. I will incorporate your comments and send you a second proof, so you can be sure I understood you. Is a week long enough? ~~ Paul At 8/5/2020 02:16 PM, John Byrd wrote: >I'd like to collaborate, if you point me at your tree. Like you,

Surprised to know that backward compatibility is not honored across the tools. (i.e. you can read old .bc but NOT old .ll files) Supporting latter is more useful, IMO, because then I wouldn't have to modify all my sources. And who are "we" here? On Fri, Aug 12, 2016 at 7:21 PM, Tim Northover <t.p.northover at gmail.com> wrote: > On 12 August 2016 at 06:42, Madhur

Hi, For my input file I think that llvm-as is encoding an instruction incorrectly. Is there any way to dump the numerical representation of input textual LLVM IR on terminal? "-f" option to llvm-as did not help. -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar

Hi, How does LLVM identify induction variables of a loop? Is the algorithm based on SSA graphs? I have a complicated loop and I need to do some analysis around it. Can anyone please point me to source of identification part? -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar

I was wondering today whether the TableGen DAG support would be more useful if you could manipulate DAGs a little more easily. Right now, you can: * Specify a DAG with (...) * Catenate DAGs with !con(). * Construct a DAG with !dag(). * Iterate over a DAG with !foreach(). * Get and set the DAG operator with !getop() and !setop(). What if you could also get and set a DAG's operands

Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin > On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > AFAIK, no official doc. > You can probably get better help if you ask specific questions (which part of the code you don't understand). > > On Thu, Jul 6, 2017 at 9:53

Thank You.. I am asking to generate directly PTX code automatically or by directives without involvement of CUDA. This way, I am talking about avoiding source to source compiler approach where c code is converted automatically into CUDA, instead I am saying directly to convert C code to PTX assembly. On Tue, Dec 11, 2018 at 12:19 PM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote:

I had another idea for a TableGen tracing feature and would like some feedback. It's quite possible I'm on the wrong track here and that improved backend tracing is what folks really need. The idea is to add a -trace option to the tblgen command line. With it you can list one or more record names. TableGen would produce a detailed trace of how the record is built: class inheritances,

Hi all, I have the below input define i32 @myCas(i32* %ptr, i32 %cmp, i32 %val) #0 { entry: %0 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %val seq_cst %1 = extractvalue { i32, i1 } %0, 0 ret i32 %1 } When I provide this input file to llvm-as 3.6 I get the error a.ll: error: Expected ordering on atomic instruction %1 = extractvalue { i32, i1 } %0, 0 This is because instruction syntax

Hi, Sorry I took a long time to reply as it took me some time to get some understanding of the code even to ask some specific questions (I have a test case in which LSR does not kick in and wanted to understand the code to figure out why it was not kicking in). Here are some specific questions I have: 1) It appears that LSR works only for the inner-most loop. Is this correct? Can you tell

Hi, My name is Venugopal Raghavan and I work in AMD. I was trying to understand the code in the file LoopStrengthReduce.cpp but I am making very slow progress. Is there any additional documentation available that would help me understand the code, like a PPT presentation or a design document or maybe a paper? I did not find anything on the Internet. There are comments interspersed in the code

Adding -debug to a -gen-dag-isel run can also print useful information about the parsed patterns. On Wed, Jul 15, 2020 at 10:44 AM Matt Arsenault via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > > On Jul 15, 2020, at 13:33, Rotate Right via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Is there a backend to Tablegen which can dump a map of

> On Apr 11, 2017, at 10:25 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I am interested in knowing more. > 1. What benchmarks does LLVM community use for compile-time study? I see CTMark, but is that the only one being analyzed? CTMark is not cast in stone. Its purpose is for the community to have a trackable proxy for the overall llvm test

Are all the records collected as they are parsed, with template parameter substitution and lets, and *then*, after all records are collected, a "pass" is made to calculate the inter-field expressions? Once I understand this, I will add a section to the new guide to explain it. I presume it is the case that this behavior should be publicized. It also appears to be the case that a record

Nobody blames ptxas. I'm not saying that these are the troubles, I'm just saying that it has some features and we have some problems to be solved. But lack of labels, label arithmetics in DWARF sections is the real problem, because LLVM actively uses it in DWARF sections Best regards, Alexey Bataev 8 нояб. 2017 г., в 5:35, Madhur Amilkanthwar <madhur13490 at