similar to: RISC-V LLVM Sync Up - 6 Aug 2020

For background on these calls, see <http://lists.llvm.org/pipermail/llvm-dev/2019-September/135087.html>. Reminder: the purpose is to co-ordinate between active contributors. If you have support questions etc then it's best to post to llvm-dev. We have a call each Thursday at 4pm GMT, via <https://meet.google.com/ske-zcog-spp>. I've created a shared calendar which may help

Hi, Sam. I think that it's a fair comparison. Keep in mind that the GP is only used to reach global variables of local scope and the GOT, where the address of global variables of global scope reside. This model assumes that the distance between the GP and the global data area, GOT and local scope variables is defined at link time. __ Evandro Menezes ◊ SiFive ◊ Austin, TX > On Mar

If I’m following correctly, there are two size-limited areas. One area, limited to 2GB, is the “text” area. This contains all the code. Then there’s a “global” area, limited to 4GB, which is pointed to by the global pointer. This contains the GOT, plus a flexible area that the object file can stick small bits of data into. And then outside of both of those, additional data is unlimited. It

For background on these calls, see <http://lists.llvm.org/pipermail/llvm-dev/2019-September/135087.html>. Reminder: the purpose is to co-ordinate between active contributors. If you have support questions etc then it's best to post to llvm-dev. We have a call every alternate Thursday at 4pm GMT, via <https://meet.google.com/ske-zcog-spp>. We have a shared calendar which may help

Oh, I wasn’t really thinking about devices without an MMU where the addresses are physically separated. Makes sense. This reminds me of rwpi on ARM; it has a sort of similar scheme of referring to data indirectly through a pointer, but it also changes the ABI to keep the pointer in a reserved register. -Eli From: Evandro Menezes <evandro.menezes at sifive.com> Sent: Friday, March 20, 2020

Hi all, The 3rd HelloLLVM social in China will happen on July 28, 2018. The location is at Hangzhou, Zhejiang. Everyone interested in LLVM related projects is invited to join. Event details is at https://mp.weixin.qq.com/s/Ruf3Dx3GBW37LnUzbfKfNA BoF style. Presentations are welcome too :-) Looking forward to meet you ! -- Best wishes, Wei Wu (吴伟)

FYI they organize this kind of stuff throughout the years in different cities. Not sure about Nanjing but I did see one in Shanghai Zhang > 在 2018年7月20日，10:40，Shi, Steven via llvm-dev <llvm-dev at lists.llvm.org> 写道： > > Is there similar social party in other Chinese cities? Like Shanghai, Nanjing? > > Thanks > Steven Shi > >> -----Original Message-----

Hello, I'm running mixed models in GAMM4 with 2 (non-nested) random intercepts and I want to include a spline term for one of my exposure variables. However, when I include a spline term, I always get reported degrees of freedom of less than 1, even when I know that my spline is using more than 1 degree of freedom. For example, here is the code for my model: >

Hi Devs, since risc-v has a register $tp which is thread pointer. is it possible to have __builtin_thread_pointer for RISC-V? I am not sure what could be corresponding instructions? ./kamlesh

Hi, I'm not a programmer, so I have a question about R functions, I run the Random Forest regression models, but I would like to run the random forest model 1000 times with different random sample set. to check the uncertainty of the regression model estimates. exemple of data: ################################# table= all Y: all$AGB X variables: Variables=as.matrix(all[, c( "min",

This approximately follows my understanding and expectation. I think that, if you have commit access, commits to improve release notes fall under the contribution guidelines for documentation and therefore do not require a full Phabricator review. I know Alex Bradbury tries to coordinate the RISC-V backend-related release notes based on the backend changes since the last release, and this seems

Hi all developers, I'm changing compiler from gcc to llvm on a RISCV target now. but I found in some case the assembly code generated by llvm is much more than gcc. It cause my program's performance about 40% decrease. The flowing is a simple test code. It shows the problem. We can see than gcc prefer to use pointer to iterate the array, but llvm perfere to use index to iterate

Thanks. I have checked the hook DAGCombiner::isMulAddWithConstProfitable And I think the above condition is too aggressive. // If the add only has one use, this would be OK to do. if (AddNode.getNode()->hasOneUse()) return true; Shall we make it to if (AddNode.getNode()->hasOneUse() && TargetLowering.isCheaperCommuteAddMul(......)) return true; The virtual hook

Something that would be good to get clarity on: The RISC-V backend recently had a bugfix patch that got backported to the 10.0.1 branch. The original patch introduced a new virtual method in TargetLowering.h, and the backported patch [1] was rewritten to avoid changing the ABI of libLLVM.so. This feels like some kind of policy decision about the C++ ABI beyond "it's entirely

Eh - I'd say "Big" new features (hey, LLVM supports DWARFv5, or Split DWARF, or DWARF type units, or DWARF compression (though I don't think I wrote any release notes for several of those features that I implemented)). I wouldn't bother release noting changes in output format for tools we don't consider to have stable output, or changes in robustness/better error

Yes - this has been in InstCombine for a long time: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp#L268 We could say that the canonicalization should be reversed, but that probably uncovers more missing optimizations. The code size concern is legitimate. For example on x86, gcc asm is 2 bytes smaller on this example:

Hi all, I met this error(title) when i was trying to compile llvm-gcc-4.2-2.7 on loongson2f,a mips compatible platform.I also failed to build a cross-compiler and the error message was the same . Is that means llvm-gcc cannot support mips back-end now? Thanks. Here is my configure options: $export TARGET=mips64el-unknown-linux-gnu $../../src/llvm-gcc-4.2-2.7.source/configure

Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V

Thank you for both of your input. Yes, I try to cross-compile for AVR, the simple ATMEGA328P used in every Arduino Uno. My main motivation being that I hope to be able to use a couple of STL containers, <functional> and <type_traits> on the MCU. Not sure though if this can be reached by going via the clang route. Getting back to the compilation: when I run clang with both both

Michael, Apologies for taking so long to get back to you. Trunk LLVM does not contain support for code generating the V extension yet. The experimental-v support you see there is only MC-layer support, where you can use the V instructions in assembly (including inline assembly). There is currently (today) no way of turning LLVM IR vector intrinsics into RISC-V V extension instructions. Hanna