similar to: is a MachineBasicBlock a kind of superblock?

Thank you for your reply! > Every MachineBasicBlock has a list of successors; you can access it with > the successors() accessor. That's what you should be using for any CFG > analysis. I am aware of these methods of class MachineBasicBlock, which allows one to access a MachineBasicBlock's successors and predecessors in the CFG. But the CFG itself may no longer be valid if a

Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty

Hi, In PHI node elimination pass to insert the copy in the predecessor block, there is a check if terminator is not an invoke instruction then place the copy there only. However for invoke terminator instruction a safe position is located for copy insertion. My doubt is why is this safe location search done only for invoke instruction and not for other terminators such as branch.

On 11/12/2009, at 10:43 AM, Anton Korobeynikov wrote: > Hi, Chris > >> That is target independent code, so you should not put sparc specific changes there. It sounds like one of the sparc-specific target hooks is wrong. > Since sparc does not provide any hooks for operation of branches (e.g. > AnalyzeBranch and friends) it might be possible that generic codegen > code is

Hi All, For various obscure reasons I'd like to detect the condition when X86 CALL instruction immediately precedes a function epilogue in the final emitted code, and insert a NOP between them if that happens. My initial attempt at it looked like this: MachineBasicBlock& MBB; MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would be inserted if (MBBI != MBB.begin()

Hi, In the LiveIntervalAnalysis::runOnMachineFunction, there is a code to compute the MBB2IdxMap, by remembering for each MBB its start and end instruction numbers: unsigned MIIndex = 0; for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); MBB != E; ++MBB) { unsigned StartIdx = MIIndex; for (MachineBasicBlock::iterator I = MBB->begin(), E =

On Feb 8, 2010, at 12:37 AM, Nathan Keynes wrote: > Firstly, the BNE/BA pair should be reduced to a BE (I assume this is > the responsibility of AnalyzeBranch and friends that you mention). Right. Implementing AnalyzeBranch will allow a bunch of block layout and branch optimizations to happen. > However I still wouldn't have expected that to result in the label > being

Sachin.Punyani at microchip.com wrote: > > Hi, > > > > In PHI node elimination pass to insert the copy in the predecessor > block, there is a check if terminator is not an invoke instruction > then place the copy there only. However for invoke terminator > instruction a safe position is located for copy insertion. > > > > My doubt is why is this safe

On Jul 3, 2009, at 4:01 AM, Sanjiv Gupta wrote: > Sachin.Punyani at microchip.com wrote: >> >> Hi, >> >> >> >> In PHI node elimination pass to insert the copy in the predecessor >> block, there is a check if terminator is not an invoke instruction >> then place the copy there only. However for invoke terminator >> instruction a safe

Hello, I was looking at how the memory for MachineBasicBlocks is managed and something seems strange. On one hand, a MachineFunction uses a recycling allocator to create and destroy MBBs without costly heap allocation (the same is done for MachineInstrs, MachineOperands, etc.). On the other hand, each MBB also has a number of STL vectors within it. For example, for Predecessors, Successors,

On 09/02/2010, at 3:57 AM, Chris Lattner wrote: > On Feb 8, 2010, at 12:37 AM, Nathan Keynes wrote: >> Firstly, the BNE/BA pair should be reduced to a BE (I assume this is the responsibility of AnalyzeBranch and friends that you mention). > > Right. Implementing AnalyzeBranch will allow a bunch of block layout and branch optimizations to happen. > >> However I still

Hi John, It looks pretty good. Thanks for working on this. Some comments: 1. Some of the functions that you introduced, e.g. stringifyCSRegSet probably ought to be "static" and ifdef'ed out when NDEBUG is defined. 2. + // DEBUG + if (! MBB->empty() && ! CSRUsed[MBB].intersects(restore)) { + MachineInstr* MI = BeforeI; + DOUT <<

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (???) MachineInstr *

Hi I'm seeing something probably related to this. I'm getting an assert from the lower_bound in LiveIntervals::findLiveinMBBs (from a checking std:: VS2005 implementation). Idx2MBBMap has two elements in it, both of which have a .first of 0. (I believe because of an empty MBB in the function below, so StartIndex doesn't advance). scott On Wed, Apr 16, 2008 at 2:52 AM, Roman

Can you file a bug so I don't forget? I'm a little occupied right now. But I'll take care of this soon. Evan On Apr 16, 2008, at 10:52 AM, Scott Graham wrote: > Hi > > I'm seeing something probably related to this. I'm getting an assert > from the lower_bound in LiveIntervals::findLiveinMBBs (from a checking > std:: VS2005 implementation). Idx2MBBMap has two

On Tue, Oct 18, 2011 at 2:59 PM, Cameron Zwarich <zwarich at apple.com> wrote: > On Oct 18, 2011, at 2:53 AM, Chandler Carruth wrote: > > > Hello, > > > > I'm working on basic-block placement optimizations based on branch > probability information. I've run into a stumbling block though. One of the > existing passes to do this, essentially a dead pass

On Tue, Oct 18, 2011 at 6:58 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Oct 18, 2011, at 5:22 PM, Chandler Carruth wrote: > > As for why it should be an IR pass, mostly because once the selection dag >> runs through the code, we can never recover all of the freedom we have at >> the IR level. To start with, splicing MBBs around requires known about

Dear llvmers, I am trying to insert a move instruction where both source and destination registers are physical registers. How is the code for this? I tried this one here: void PhiDeconstruction_Fer::add_move ( MachineFunction & mf, MachineBasicBlock & mbb, unsigned

On Tue, Oct 18, 2011 at 4:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Oct 18, 2011, at 3:07 PM, Chandler Carruth wrote: > > On Tue, Oct 18, 2011 at 2:59 PM, Cameron Zwarich <zwarich at apple.com>wrote: > >> I think this should really live as a CodeGen pass. Is there any good >> reason to make it an IR pass? >> > > So, as it

Here is an updated patch for shrink wrapping with: - spills/restores done with stack slot stores/loads - stack adjustment removed - refactoring (but still in need of more) - spill/restore insertion code unified with spill/restore placement code Documentation available here<http://wiki.github.com/jdmdj/llvm-work/shrink-wrapping-work> illustrates shrink wrapping with loops and discusses a