similar to: [RFC] C++20 ABI issue on several platforms

Richard Sandiford wrote: >I'd like to step down as code owner for the SystemZ port and nominate >Ulrich Weigand to take over. Sorry for not doing this sooner. I'd be happy to take over that role. Thanks for all your work on SystemZ, Richard! Bye, Ulrich

Andrew Kaylor wrote: >In general, the current "strict FP" handling stops at instruction >selection. At the MachineIR level we don't currently have a mechanism >to prevent inappropriate optimizations based on floating point >constraints, or indeed to convey such constraints to the backend. >Implicit register use modeling may provide some restriction on some

> On Jan 9, 2018, at 1:53 PM, Kaylor, Andrew via cfe-dev <cfe-dev at lists.llvm.org> wrote: > > I think we’re going to need to create a new mechanism to communicate strict FP modes to the backend. I think we need to avoid doing anything that will require re-inventing or duplicating all of the pattern matching that goes on in instruction selection (which is the reason we’re

> > I'm not sure why this is an issue. Yes, these two intrinsics depend > on the current rounding mode according to the C standard, and yes, > LLVM in default mode assumes that the current rounding mode is the > default rounding mode. But the same holds true for many other > intrinsics and even the arithmetic IR operations like add. Any other intrinsic, like `floor`,

Hans Wennborg wrote: >Dear testers, > >8.0.0-rc4 was just tagged from the release_80 branch at r355690. I've tested the current branch on SystemZ without problems. I noticed I forgot to send a ReleaseNotes updates, sorry. If there's still time, here's a list of the major user-visible changes: (See attached file: systemz-releasenotes.diff) Mit freundlichen Gruessen / Best

I am trying to calculate the median of each row of a data frame where the data frame consist of columns of class Date. Below are my test data and best attempt at using apply. I didn't see a solution via Google or the Baron search site. I'd be grateful for any suggestions or solutions. I'm using R 2.0.0 on Mac OS X. Thank you, Stephen Weigand ### Test data date1 <- c(1000,

Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote on 25.04.2013 18:58:05: > On Apr 25, 2013, at 4:44 AM, Ulrich Weigand <Ulrich.Weigand at de.ibm.com> wrote: > > > Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote on 24.04.2013 23:47:54: > > > >> I would like to add one more case here: Fixed register operands. > >> > >> Some

I think we're going to need to create a new mechanism to communicate strict FP modes to the backend. I think we need to avoid doing anything that will require re-inventing or duplicating all of the pattern matching that goes on in instruction selection (which is the reason we're currently dropping that information). I'm out of my depth on this transition, but I think maybe we could

On 10.12.2012, at 15:19, Ulrich Weigand <Ulrich.Weigand at de.ibm.com> wrote: > Chandler Carruth <chandlerc at gmail.com> wrote: > >> I've been working to revive the PPC64 build bots, and succeeded, but >> not for the right reasons. There were still bootstrap assertion >> failures and other pretty blatant errors. Then we figured out why: >> the Clang

Csaba Raduly <rcsaba at gmail.com> wrote: > error: no disassembler for target s390x--linux-gnu The SystemZ disassembler was only recently added. To process major changes to the source tree like the addition of a completely new component, it seems to be necessary to explicitly re-run configure (or sometimes even remove the build directory completely and start from scratch). I've

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Hi Hal, I only just noticed that about a year ago, Jim removed CPU auto-detection for the X86 target: http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-April/071991.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140407/212676.html >Currently the X86 backend does CPU auto-detection and subtarget feature >detection when the TargetMachine is created if no explicit CPU was

Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote on 24.04.2013 23:47:54: > I would like to add one more case here: Fixed register operands. > > Some instructions, like x86's MUL and DIV, take operands in fixed > registers. Currently, we handle that with COPY instructions to and > from the fixed registers, but that is making code motion passes more > complicated than

On 9 Jan 2018 22:55, "John McCall via llvm-dev" <llvm-dev at lists.llvm.org> wrote: On Jan 9, 2018, at 3:50 PM, Kaylor, Andrew <andrew.kaylor at intel.com> wrote: >The standard argument against trying to introduce "scope-like" mechanisms to LLVM IR is inlining; >unless you're going to prevent functions that use stricter/laxer FP rules from being inlined

On Tue, Jan 09, 2018 at 06:53:51PM +0000, Kaylor, Andrew via cfe-dev wrote: > I think we're going to need to create a new mechanism to communicate > strict FP modes to the backend. I think we need to avoid doing anything > that will require re-inventing or duplicating all of the pattern > matching that goes on in instruction selection (which is the reason >

Benjamin Kramer <benny.kra at gmail.com> wrote on 11.12.2012 12:48:55: > On 10.12.2012, at 15:19, Ulrich Weigand <Ulrich.Weigand at de.ibm.com> wrote: > > Maybe I'm confused somehow, but I thought this one: > > http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2 > > does bootstrap and then run both LLVM and Clang tests (successfully): > >

>The standard argument against trying to introduce "scope-like" mechanisms to LLVM IR is inlining; >unless you're going to prevent functions that use stricter/laxer FP rules from being inlined >into >each other (which sounds disastrous), you're going to need to communicate strictness on an >instruction-by-instruction basis. If the backend wants to handle that by

Hi Ulrich, and any other llvm PowerPC/JIT users, It looks like the Numba maintainers have run in to an issue with RuntimeDyldELF's PowerPC support (See https://github.com/numba/numba/issues/2451#issuecomment-377739948 and later comments) Due to a recent change to weak symbol handling, we now always resolve to the first copy of a function that is emitted (discarding redundant weak/odr

Gabor Greif <ggreif at gmail.com> wrote: > as of v3.3 the integrated assembler seems to work fine. > But it is not on by default. What is the obstacle for this last step? Well, it's support is not complete ... The integrated assembler supports all general-purpose instructions the compiler itself generates, but has only partial support for all the rest, in particular nearly no

Hi PPC folks, as of v3.3 the integrated assembler seems to work fine. But it is not on by default. What is the obstacle for this last step? Just curious, Gabor