similar to: Handling far branches with fixups or ELF relocs

Hi all, In RISC-V ISA, the range of conditional branches is within 4KiB. In current implementation, if the branch target is out of range, LLVM MC will issue an error message to tell users it could not resolve the fixup record. I have compared the result with the GNU assembler. GNU assembler will convert the branch to inverted one plus jump to make the branch possible. The range of unconditional

This sounds very similar to what PowerPC does, see: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp However, PowerPC is doing this in the compiler backend, not in the assembler. One issue is that the process must be iterative, because branches can go both forward and backward, and replacing some branch instructions with the branch pairs can then

Hi all. There are two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169) Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V,

I met with the Propeller team today (we work for the same company but it was my first time meeting two members on the team:) ). One thing I have been reassured: * There is no general disassembly work. General disassembly work would assuredly frighten off developers. (Inherently unreliable, memory usage heavy and difficult to deal with CFI, debug information, etc) Minimal amount of plumbing work

Hi, For the following code: void foo (); int main () {foo();} llvm emits "bl foo" Then I set foo at a far address in linking: aarch64-linux-gnu-gcc -Wl,--defsym=foo=0x80000000 a.o -o a.exe I got an error from ld: a.c:(.text+0x8): relocation truncated to fit: R_AARCH64_CALL26 against symbol `foo' define in *ABS* section in a.exe The question is: do I

David Blaikie <dblaikie at gmail.com> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per file in a compilation and resolve > correctly when one object file is built with one ABI and another object > file is built with a different ABI (that seems to be antithetical to the > concept of "ABI" Though) - then it should be a subtarget feature. > > ABI is

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to

I also work on the RISC-V backend, and have been doing a little work on the ELF psABI document for RISC-V. I agree that, conceptually, the psABI choice should be in the module metadata. Zakk, however, has discovered a phase ordering issue within LLVM that relates to this approach. The phase ordering problem is that the LTO backend is currently setup without interrogating the current module for

> On Jan 6, 2020, at 14:29, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > On Mon, Jan 6, 2020 at 5:58 AM Zakk <zakk0610 at gmail.com <mailto:zakk0610 at gmail.com>> wrote: > > > David Blaikie <dblaikie at gmail.com <mailto:dblaikie at gmail.com>> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per

David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> 於 2020年1月11日 週六 上午2:03寫道： > Ah, OK - thanks for walking me through that. > > Fair enough, I think I understand the issue/tradeoff now - and that the > other module level metadata don't currently influence the target > configuration at this level? > > I'm not sure, I only know that the target-abi is decided

David Blaikie <dblaikie at gmail.com> 於 2020年1月14日 週二 上午2:15寫道： > > > On Mon, Jan 13, 2020 at 6:12 AM Zakk <zakk0610 at gmail.com> wrote: > >> >> >> David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> 於 2020年1月11日 週六 >> 上午2:03寫道： >> >>> Ah, OK - thanks for walking me through that. >>> >>> Fair enough, I

On Tue, Jan 7, 2020 at 5:27 PM Eric Christopher <echristo at gmail.com> wrote: > > > On Tue, Jan 7, 2020 at 3:18 PM Daniel Sanders via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Jan 7, 2020, at 13:57, David Blaikie <dblaikie at gmail.com> wrote: >> >> >> >> On Mon, Jan 6, 2020 at 6:05 PM Daniel Sanders

Right. I think that's what we ended up doing rather than a more general attribute on the module itself. *shrugs* Probably ok? I'd probably prefer not to have to have target code to do the evaluation if possible, but everything is weird and an edge case - mips abis more than some :) -eric On Wed, Jan 8, 2020 at 8:58 AM David Blaikie <dblaikie at gmail.com> wrote: > Oh, I should

On Mon, Jan 20, 2020 at 8:05 AM Sam Elliott via llvm-dev < llvm-dev at lists.llvm.org> wrote: > To follow up on this issue: > > Our plan is still to encode `target-abi` into the module flags for RISC-V > LLVM IR modules. As was pointed out earlier in this thread, the function > lowering in Clang is slightly different for the ABIs which support hardware > floating point.

Hi all, Continuing work on llvm-ml (a MASM assembler)... and my latest obstacle is in enabling MASM's convention that (unless specified) all memory location references should be RIP-relative. Without it, we emit the wrong instructions for "call", "jmp", etc., and anything we build fails at the linking stage. My best attempt at this so far is a small patch to

On Mon, Jan 27, 2020 at 3:04 PM Eric Christopher <echristo at gmail.com> wrote: > > > On Mon, Jan 27, 2020 at 2:56 PM David Blaikie via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Mon, Jan 20, 2020 at 8:05 AM Sam Elliott via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> To follow up on this issue:

Apologies - I apparently remembered part of the issue incorrectly, so this ended up quite confusing. The problem comes when referencing labels in a different section of the binary. To clarify, if I assemble the code: .data foo BYTE 5 .code mov eax, foo with Microsoft's ml64.exe, it emits an object file disassembling to: 0: 8b 05 00 00 00 00 mov eax, dword ptr [rip]

Are you asking what the parsing rules are, or how you should modify the LLVM code to achieve that result? If the latter, you haven’t really given enough detail here. What code, exactly, have you tried modifying? Do you have any ideas for how it could work? -Eli From: Eric Astor <epastor at google.com> Sent: Tuesday, January 21, 2020 2:44 PM To: Eli Friedman <efriedma at

Hi, I've seen on the LLVM's Open Projet Page [1] an idea about using LLVM to generate native code in Valgrind. For what I know, Valgrind uses libVEX to translate native instructions into a bitcode, used to add the instrumentation and then translated back to native code for execution. Valgrind and LLVM are two tools that I use nearly every day. I'm also very interested in code

> On Jan 7, 2020, at 13:57, David Blaikie <dblaikie at gmail.com> wrote: > > > > On Mon, Jan 6, 2020 at 6:05 PM Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > > >> On Jan 6, 2020, at 14:29, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: