similar to: How to implement load/store for vector predicate register

Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a

Hi All, I *think* it's ddply because the function recognizes vr1, etc, in other parts of the function. Here's some code: # create dataset PROV.PM.FBCTS <- c(0.00 ,0.00, 33205.19, 25994.56, 23351.37, 26959.56 ,27632.58, 26076.24, 0.00, 0.00 , 6741.42, 18665.09 ,18129.59 ,21468.39 ,21294.60 ,22764.82, 26076.73) FBCTS.INV.TOT <- c(0 , 0, 958612, 487990, 413344, 573347,

On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>> %sum = fadd %tx, %ty >>> %newvalue

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;

Ah, I think I get it now. This was mentioned earlier in the thread, but it didn't click at the time. It sounds like I can do instruction selection with a pattern like (omitting selection of the sources): let Constraints = "$dst = $oldvalue" in { def MASKEDARITH : MyInstruction< (outs VectorReg:$dst), (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,

On Dec 2, 2011, at 12:40 PM, Evan Cheng wrote: > There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Let me add some

. and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier.. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Friday, December 02, 2011 2:40 PM To: LLVM Dev Subject: [LLVMdev]

On Dec 2, 2011, at 2:41 PM, Sergei Larin wrote: > … and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier…. Isn't that just the order of the instructions in the list? I don't see anything that prevents getting the order of instructions. It might require iterator over MIs in the packet. But for

Evan, I will need to comprehend it better, but one small comment right away. Did we not discuss one more option for bundle implementation - global cycle ID. We would add an unsigned int field to MI definition representing "global scheduling cycle". All MIs with the same global cycle value belong to one group/packet. Zero means unscheduled MI. That is light weight,

Hi Evan, I just read your proposal and the following discussion for VLIW support and want to share my experience of writing a VLIW back-end for LLVM. I would not integrate the packetizer into the register allocator super class since it would reduce the flexibility for the back-end developer to add some optimization passes after the packetizer. Instead, I would add the packetizer as a separate

On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether

Machine Instruction Bundle in LLVM Hi all, There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Design Criteria 1. The

Hi Everyone, I have pfSense running which supplies Asterisk with DHCP. I had some testing ports opened for a web server which I have totally closed now but when I chose option 10 (filter log) on pfSense I get all of this type of traffic (note that it was only 1 single IP and once I blocked that one it was like opening a can full of bees with all different IPs): tcpdump: WARNING: pflog0: no

I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the

Hello, Freebsd-stable. BIND on my new router (7.1-STABLE, BIND 9.4.3-P1) shows bunch of errors on every start and doesn't answer on requests for 30-60 seconds after that. Errors are like this: Jan 24 12:18:12 gateway named[1455]: /usr/src/lib/bind/isc/../../../contrib/bind9/lib/isc/unix/socket.c:1567: unexpected error: Jan 24 12:18:12 gateway named[1455]: internal_send: 193.0.14.129#53:

I have a question about how to reference variables in a dataframe. Normally, after I have read in some Stata data using the following command all <- read.dta('all.dta') Whenever I want to use the variable "sat.vr1" in the "all" data frame, I do so using all$sat.vr1 However, I'd like to be able to use the sat.vr1 variable without the "all$" (as well

Hi. If I have a vector, v_1, and another vector of positive integers, i_1, the same length as v_1, then rep(v_1,i_1) will repeat v_i[j] exactly i_1[j] times, like so: >rep(c(1,2,3),c(3,2,1)) [1] 1 1 1 2 2 3 > I'd like to do the same sort of thing where I replace v_1 with a matrix, and the jth row of the matrix is repeated i_1 times. Obviously, I could do this with for loops, like

Hi, I am writing an analysis pass for a custom processor. I get an unusual situation where the code generated for a BB is BB#23: derived from LLVM BB %sw.bb99 Live Ins: %vr2 %vr0 %vr1 %vr9 %vr3 %vr8 %vr4 %vr5 %vr6 Predecessors according to CFG: BB#22 %vr46<def> = LD_Iri %LV, -4; mem:LD4[FixedStack0] %vr7<def> = ADDri %vr9, 1 %vr47<def> = ADDri

Hi all, I'm trying to create a new volume in a netfs pool. The pool works correctly and it is active. If I try to create the volume from the virt-manager GUI nothing happens. While if I use virsh this is the result. *virsh # pool-list * *Name State Autostart * *-----------------------------------------* *routers active yes * * * *virsh #

Hello, I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class