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I wanted confirm answer from you guys. Request you to provide authentic information on this. Best Regards / Mit freundlichen Grüßen Minal Kulkarni Knorr Bremse Technology Center India Survey No.276, Village Mann, Hinjewadi, Phase II, Tal.Mulshi, Pune - 411 057. Maharashtra , India. Phone: +91 9028098122 Mobile: mailto:minal.kulkarni at knorr-bremse.com

>>Dear Users, >> >>I use KVM with libvirt 9.0.0. The host and guest OS-es are also AGL needlefish images. I am currently trying to virtualize a CAN driver and provide virtual machines access to the physical CAN channels. >> >>I started with the virtual network handling as CAN interface is a network interface, I tried to find analogies, solutions like

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 knorr smbd[5439]: [2003/10/31 10:27:02, 0] lib/util_sock.c:get_socket_addr(919) knorr smbd[5439]: getpeername failed. Error was Transport endpoint is not connected knorr smbd[5439]: [2003/10/31 10:27:02, 0] lib/util_sock.c:write_socket_data(388) knorr smbd[5439]: write_socket_data: write failure. Error = Connection reset by peer knorr smbd[5439]:

Hi, search on web indicates that R also includes a hist method on POSIXct vectors. My (perhaps too unexperienced) approach below yields an error. Could somebody give me a hint what's wrong ? Peter > str(samples) `data.frame': 7500 obs. of 1 variable: $ DateTime:'POSIXct', format: chr "2006-07-20 00:10:08" "2006-07-20 00:11:17" "2006-07-20

Hi, I have a casting/formatting question on hist.POSIXt: The histogram plot from POSIXct works perfect (with help of Prof. Ripley -thanks!). When processing the hist(plot=FALSE) output and then plotting the results over the x-axis (bins) coming from hist(), I lose the date/time labels, getting instead integers displayed. Trying to cast the $breaks with as.POSIXct gives silly results with

Hi all.. I'm very new R, and i'm analyzing microarray data using Bioconductor.. Recently i was given microarray data to analyze. The problem is whenever i run MAS5 presence calls algorithm, it throws an error saying NA/NaN/Inf in foreign function. How do i remove such NA/NaN/Inf's ?? I tried na.omit(dataframe) but stil problem exists. dimension of matrix (data) is 35556 7. >

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, all. Last night, access to our samba server was interrupted, and the only thing I can find is these repeated over and over again in the messages file: Jul 8 07:44:15 knorr winbindd[24628]: cli_pipe: return critical error. Error was NT_STATUS_PIPE_DISCONNECTED Jul 8 07:44:15 knorr winbindd[24628]: [2005/07/08 07:44:15, 0]

I have the following in my functional test file. class UserControllerTest < ActionController::TestCase fixtures :users def setup @controller = UserController.new @request = ActionController::TestRequest.new @response = ActionController::TestResponse.new @invalid_user = user(:invalid_user) @valid_user = users(:valid_user) end def test_login_success

Hi Eli, >>>> 2. Storing arbitrary sized integers >>>> >>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>> loading/storing e.g. i33 integers from/into global variable. The >>>> questions are the same as regarding feature 1: How important is this >>>> feature? Is it save to ignore it? Is there

Fabian, > here are the definitions of these register classes: > > // Data register class > def DR : RegisterClass<"TriCore", [i32], 32, > (add D0, D1, D2, D3, D4, D5, D6, D7, > D8, D9, D10, D11, D12, D13, D14, D15)>; > > // Extended-size data register class > def ER :

I have a AJAX based form and when I use send_file there is no pop-up that appears to prompt user to download file... how do I fix this? Regards, Sudhindra -- Posted via http://www.ruby-forum.com/. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "Ruby on Rails: Talk" group. To post to this group, send email

Hi Fabian, Anton, On 22/08/2012 08:25, Fabian Scheler wrote: >>> here are the definitions of these register classes: >>> >>> // Data register class >>> def DR : RegisterClass<"TriCore", [i32], 32, >>> (add D0, D1, D2, D3, D4, D5, D6, D7, >>> D8, D9, D10, D11, D12, D13, D14,

Hi Eli, thank you for the information. >> thanks to kind help of the LLVM-community I was able to bring my >> TriCore back-end a huge step forward, however I am not done, so far. I >> still miss the following features and maybe you could again provide me >> some help: >> >> 1. Passing return values on the stack >> >> Describing the calling

On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hi Eli, > >>>>> 2. Storing arbitrary sized integers >>>>> >>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>>> loading/storing e.g. i33 integers from/into global variable. The >>>>> questions

Hi LLVM-Folks, at our department we have an in-house developed back-end for the TriCore processor and we want to upgrade it to LLVM 3.1. However, we have some troubles regarding some instructions that work on 64bit registers: The TriCore processor has 16 32bit registers that can be paired to form 64bit registers. Except a few instructions all work on 32bit registers, thus the TriCore processor

2012/8/20 Eli Friedman <eli.friedman at gmail.com>: > On Mon, Aug 20, 2012 at 12:01 AM, Fabian Scheler > <fabian.scheler at gmail.com> wrote: >> Hi Eli, >> >>>>>> 2. Storing arbitrary sized integers >>>>>> >>>>>> The testcase "test/CodeGen/Generic/APIntLoadStore.ll" checks for >>>>>>

On Thu, Aug 16, 2012 at 11:48 PM, Fabian Scheler <fabian.scheler at gmail.com> wrote: > Hi Eli, > > thank you for the information. > >>> thanks to kind help of the LLVM-community I was able to bring my >>> TriCore back-end a huge step forward, however I am not done, so far. I >>> still miss the following features and maybe you could again provide me

>> here are the definitions of these register classes: >> >> // Data register class >> def DR : RegisterClass<"TriCore", [i32], 32, >> (add D0, D1, D2, D3, D4, D5, D6, D7, >> D8, D9, D10, D11, D12, D13, D14, D15)>; >> >> // Extended-size data register class >> def ER :

Hi everybody, thanks to kind help of the LLVM-community I was able to bring my TriCore back-end a huge step forward, however I am not done, so far. I still miss the following features and maybe you could again provide me some help: 1. Passing return values on the stack Describing the calling conventions in tablegen so that first registers are used and to fall back to the stack if these do not

> This isn't really my area of expertise, but I think you're messing up > your RegisterClass definition. Look at how ARM defines DTriple. DTriple is untyped :) , because we do not have any valut type which defines 3xi64. However, the paired register needs to have type. Fabian, what are the definitions of ER and DR register classes? -- With best regards, Anton Korobeynikov Faculty