Displaying 20 results from an estimated 2000 matches similar to: "LLVM type.h question"
2012 Jun 10
1
[LLVMdev] Why no setAddressSpace method?
Dear LLVM,
A minor thing.
During opt passes it is sometimes needed to adjust the pointer address
space. However, I've noticed PointerType in LLVM has only get accessor, and
clang has its initial setter. Maybe better to
--- DerivedTypes.h (revision 156703)
+++ DerivedTypes.h (working copy)
@@ -450,6 +450,9 @@
/// @brief Return the address space of the Pointer type.
inline
2019 Dec 24
2
RFC: Refactor SubclassData
Hello devs,
Recently I've been working on a bug that can probably be fixed with the
addition of a simple flag to a class descendant of `llvm::Value`.
Without increasing the size of the class, I can just add this flag to
`llvm::Value::SubclassData`. But this is not an easy task!
This is because the offsetes/sizes of the data stored in the
`SubclassData`, are hardcoded literals/enums.
If you
2013 Sep 15
2
[LLVMdev] LLVM disassembler bugs
The attached patch includes no test-case and isn't consistent with the rest
of the file:
- constants should be on the right hand side of comparisons
- the braces around your single line 'if' aren't needed.
On Sun, Sep 15, 2013 at 2:39 PM, James Courtier-Dutton <
james.dutton at gmail.com> wrote:
> I attach a patch that fixes this bug. Applies to llvm 3.4svn
>
>
2013 Sep 13
3
[LLVMdev] LLVM disassembler bugs
Hi,
I am looking at the "LLVMOpInfoCallback GetOpInfo" callback.
Example 1 GOOD:
41 c6 84 24 16 04 00 00 0c : movb $12, 1046(%r12)
Makes calls to the callback with:
Offset = 0x4, Size = 0x4 <- Octets: 16 04 00 00
Offset = 0x8, Size = 0x1 <- Octets: 0c
That was correct.
Example 2 BAD:
c7 45 98 a1 ff ff ff : movl $4294967201, -104(%rbp)
Makes calls to the callback
2014 May 16
4
[LLVMdev] Writing an address space re-numbering pass?
Hi,
I'm trying to figure how to write a Module pass that globally
renumbers address space numbers e.g.
>From -> To
0 -> 1
1 -> 3
2 -> 2
3 -> 4
4 -> 999
I see that the address space number is a property that belongs to
Types[1] and that types are immutable, so I'm not sure how to
correctly implement this. But if it is I'd greatly appreciate advise
on how to do
2013 Sep 15
0
[LLVMdev] LLVM disassembler bugs
Test case attached. It is not a test case that works within the llvm
test-suite yet, but it does demonstrate the problem.
I would like some advice on how to modify this test_case so that it can be
added to the automated llvm test cases.
On 15 September 2013 23:02, David Majnemer <david.majnemer at gmail.com> wrote:
> The attached patch includes no test-case and isn't consistent
2013 Mar 15
6
[LLVMdev] Simple question
Hi,
I think this is a very simple question, and it must just be missing something.
I am looking for find out how to assign a constant integer value to
the variable in llvm ir.
The following returns 12, and %var2 = 12.
; ModuleID = 't.c'
target datalayout =
2009 Aug 03
0
[LLVMdev] RFC: SDNode Flags
I also want a way to add target specific flag to a SDNode (which
should be transferred to MachineInstr). For example, on x86 lots of
opcodes have *lock* variants. Right now, these are separate
instructions. I'd prefer to make it into a target specific flag that
can be toggled by some sort of post-isel action routine.
One way to handle this might be to expand the use of SubclassData.
2013 Mar 16
3
[LLVMdev] Simple question
On Mar 15, 2013 10:53 PM, "Óscar Fuentes" <ofv at wanadoo.es> wrote:
>
> James Courtier-Dutton <james.dutton at gmail.com> writes:
>
> > I think this is a very simple question, and it must just be missing
something.
> >
> > I am looking for find out how to assign a constant integer value to
> > the variable in llvm ir.
> >
> > The
2009 Jul 31
4
[LLVMdev] RFC: SDNode Flags
Right now the MemSDNode keeps a volatile bit in the SubclassData to mark
volatile memory operations.
We have some changes we'd like to push back that adds a NonTemporal flag
to MemSDNode to mark instructions where movnt (on x86) and other goodness
can happen (we'll also add the TableGen patterns to properly select movnt).
In our tree we simply added another flag to the MemSDNode
2012 May 07
6
[LLVMdev] Using LLVM for decompiling.
On 7 May 2012 16:31, John Criswell <criswell at illinois.edu> wrote:
> On 5/7/12 5:47 AM, James Courtier-Dutton wrote:
>>
>> Hi,
>>
>> I am writing a decompiler. I was wondering if some of LLVM could be
>> used for a decompiler.
>> There are several stages in the decompiler process.
>> 1) Take binary and create a higher level representation of it.
2013 Sep 15
0
[LLVMdev] LLVM disassembler bugs
I attach a patch that fixes this bug. Applies to llvm 3.4svn
Please commit it please.
Kind Regards
James
On 13 September 2013 17:46, James Courtier-Dutton <james.dutton at gmail.com>wrote:
> Hi,
>
> I am looking at the "LLVMOpInfoCallback GetOpInfo" callback.
>
> Example 1 GOOD:
> 41 c6 84 24 16 04 00 00 0c : movb $12, 1046(%r12)
>
> Makes
2012 Sep 13
5
[LLVMdev] [OT] Control Flow Graph(CFG) into Abstract Syntax Tree(AST)
Hi,
I know most compilers go from AST to CFG.
I am writing a decompiler, so I was wondering if anyone knew of any
documents describing how best to get from CFG to AST.
The decompiler project is open source.
https://github.com/jcdutton/libbeauty
The decompiler already contains a disassembler and a virtual machine
resulting in an annotated CFG. It uses information gained from using a
virtual
2013 Jun 28
3
[LLVMdev] Question regarding the x86 SBB instruction.
Hi,
I have the x86 SBB instruction. how should I represent this in LLVM
IR. (as part of a decompiler from binary to LLVM IR)
Pre-conditions:
%eax = 0xffffffff
%edx = 0xffffffff
%carry = 1
SBB %eax, %edx // %edx is the destination doing %edx = %edx -
(%eax + carry)
JC jump_destination1 // If the Carry flag is set, jump to jump_destination1
How do I represent this correctly in LLVM
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch 0004-Enable-HLE-code-generation.patch
Yours
- Michael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch 0002-Add-HLE-target-feature.patch
Yours
- Michael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and XRELEASE prefixes.
> To support
2013 Feb 19
0
[LLVMdev] [RFC] Add Intel TSX HLE Support
Here is the patch
0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch
Yours
- Michael
On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote:
> Hi All,
>
> I'd like to add HLE support in LLVM/clang consistent to GCC's style [1].
> HLE from Intel TSX [2] is legacy compatible instruction set extension to
> specify transactional region by adding XACQUIRE and
2017 Apr 16
2
[LLVMdev] Moving towards a singular pointer type
On Sun, Apr 16, 2017 at 2:34 AM James Courtier-Dutton via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi,
>
> Did this work ever get done? There was a long thread about it back in 2015.
>
> I wish to use IRBuilder.
> Is there any documentation?
> How do I use the singular pointer type in GEP, LOAD, STORE instructions?
>
Sorry, no, the work is not complete - for
2013 Oct 29
2
[LLVMdev] Missed optimization opportunity with piecewise load shift-or'd together?
On Mon, Oct 28, 2013 at 10:09 AM, James Courtier-Dutton
<james.dutton at gmail.com> wrote:
> My guess is that this is a missed optimization, but in real life, all
> projects i have worked fix this in the C or C++ code using macros that
> change what instructions are used based on target platform and its
> endedness.
One reason for writing code like this, i.e. explicitly spelling
2013 Feb 19
2
[LLVMdev] [RFC] Add Intel TSX HLE Support
Hi All,
I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to
specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for