similar to: Permitted success/failure orderings for atomic compare_exchange

Hi all, The C++11 (& C11) compare_exchange functions with explicit memory order allow you to specify two sets of semantics, one for when the exchange actually happens and one for when it fails. Unfortunately, at the moment the LLVM IR "cmpxchg" instruction only has one ordering, which means we get sub-optimal codegen. This probably affects all architectures which use

+Dean Michael Berris <dberris at google.com> On Wed, Jan 25, 2017 at 7:01 AM Oleg Ranevskyy via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi Renato, Dean, Serge, > > Just looked into the code and wanted to share some thoughts. > > This might be a compare_exchange_weak spurious failure. ARM is a weakly > ordered CPU, but I am not sure whether spurious failures

Hi, I've been looking at improving atomicrmw & cmpxchg code more, particularly on architectures using the load-linked/store-conditional model. The summary is that current expansion for cmpxchg seems to happen too late for LLVM to make meaningful use of the opportunities it provides. I'd like to move it earlier and express it in terms of a first-class pair of "load linked"

Currently the AtomicExpandPass will lower the following IR: define i1 @foo(i32* %obj, i32 %old, i32 %new) { entry: %v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release acquire*_ %v1 = extractvalue { i32, i1 } %v0, 1 ret i1 %v1 } to the equivalent of the following on AArch64: _*ldxr w8, [x0]*_ cmp w8, w1 b.ne .LBB0_3 // BB#1:

Hi Philip, On 29 May 2014 17:03, Philip Reames <listmail at philipreames.com> wrote: > I have some reservations about this proposal. I don't have anything > particularly concrete, but the idea of supporting both LL/SC and atomicrwm > in the IR concerns me from a complexity perspective. Well, I'll start by saying my particular optimisation use case looks like it's not

On Dec 17, 2007, at 2:25 PM, John Criswell wrote: > So, is there a way for a Pass to specify that other transforms > should be > run first, or can that only be done with PassManager.add()? PassManager.add() is the way to go. If one relies on PassManager to order transformations passes properly then we are stepping into "Find optimal ordering of optimization/ transformations

Hi! I just discovered that cutree() and cut.dendrogram() do not assign the same cluster numberings when called on the same tree. More specifically, cutree() assigns cluster numbers by order of appearance in the data, while cut.dendrogram() sorts clusters by height (see example below). I guess this is for historical reasons? I'm hit by this difference when I want to get a vector of cluster

Dear Devang Patel, In response to your comment on bug 1868, how do I get BottomPass to requires Pass2 before Pass1? Is it by reversing the order of the calls to AU.addRequired()? -- John T. -- John T. Criswell jcriswel at bigw.org "It's today!" said Piglet. "My favorite day," said Pooh.

Hi, I have the following test case: define void @foo(<2 x float>* noalias nocapture %out, <2 x float>* noalias nocapture %data0) nounwind { entry: %val1 = load <2 x float>* %data0, align 8 store <2 x float> %val1, <2 x float>* %out, align 8 fence acq_rel %val2 = load <2 x float>* %data0, align 8 store <2 x float> %val2, <2 x float>*

Devang Patel wrote: > > On Dec 17, 2007, at 2:01 PM, John Criswell wrote: > >> Devang Patel wrote: >>> >>> On Dec 17, 2007, at 1:47 PM, John Criswell wrote: >>> >>>> Dear Devang Patel, >>>> >>>> In response to your comment on bug 1868, how do I get BottomPass to >>>> requires Pass2 before Pass1? Is it by

On 7 June 2013 17:52, Dallman, John <john.dallman at siemens.com> wrote: > Is it possible for the debug information to mark all the instructions that arise > from a > language statement as coming from that statement, even though the instructions may > be widely scattered? Yes. > Instructions whose effects > are used in the logic from more than one statement would have to

On Wed, Jun 12, 2013 at 6:17 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > Hi, > > I have the following test case: > > define void @foo(<2 x float>* noalias nocapture %out, <2 x float>* > noalias nocapture %data0) nounwind { > entry: > %val1 = load <2 x float>* %data0, align 8 > store <2 x float> %val1, <2 x float>* %out,

Greetings everyone, I am working on Aarch64 LSE out-of-line atomics support in LLVM, porting this GCC series: https://gcc.gnu.org/legacy-ml/gcc-patches/2019-09/msg01034.html After local design experiments I've got some questions about upstream-suitable ways of implementation. More specifically: 1. Pass to expand atomics to library helper functions calls. These helpers test for the presence

So fence only forces ordering of atomic instructions. Let me change my question then. If I have a target-specific intrinsic which forces ordering of ordinary load/store instructions. Then should it also force ordering of load/stores to noalias pointers in caller functions? Thanks, Xiaoyi From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Wednesday, June 12, 2013 7:06 PM To: Guo,

Current precent in the codebase is the __sync_* libcalls. They have essentially the semantics you want, except that they're all seq_cst. On the LLVM side, I'd rather not have two ways to do the same thing, so I'd prefer to extend the existing mechanism. Adding 100 lines to RuntimeLibcalls.def seems a bit unfortunate, but I think you can reduce that using some C macros. On the

C++ and Java memory models impose restrictions for locks and unlocks, such as a thread that releases a lock must acquired the lock, or the number of locks must be larger than the number of unlocks in the same thread... for enabling some optimizations, for example, simplifying trylocks (http://www.hpl.hp.com/techreports/2008/HPL-2008-56.html), and moving some instructions inside lock acquires

Yeah, I was being optimistic about this one. It should be changed to strong if he weak version doesn't quite do it. The other way to do this is to change the test to do the polling, but that seems sub-optimal. Sent from my iPhone > On 26 Jan 2017, at 5:10 am, Serge Rogatch via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > Indeed, it seems that exactly this

On 28 September 2014 22:09, Hal Finkel <hfinkel at anl.gov> wrote: > Thanks Xinmin! > > So we'll need a method to ensure the correct (partial) ordering. I thought that the idea was to avoid computing loop dependencies when safelen is specified, at least at that level. We might do it to a greater length, but we should assume it to be safe for distances < VL. We still need

Sorry this is off-topic, but I'm scrambling to get this system in, google didn't help, and I'm sure someone on this list knows the answer cold. I'm trying to nfs-export a tmpfs disk. I saw a hint from a response about ram disks... which leads to my guess that tmpfs simply doesn't implement some method that nfsd needs. I can probably survive without tmpfs, but I'd like to

Hi, I am using wine-0.9.30 (self compiled) on a Debian 3.1 server. Wine is required for CUI-applications, so no X-Server is running. When I log in via ssh and start the application, wine is working fine. But whenever I try it from the webserver via php-script, wine doesn't start properly. It fills the errout with "epoll_ctl: Operation not permitted" unitl I send a SIGKILL to the