similar to: Instruction selection phase

Displaying 9 results from an estimated 9 matches similar to: "Instruction selection phase"

2020 Mar 02
3
TableGen Instruction class Uses and Defs
Hello LLVM-Dev, I understand that Uses and Defs are for implicit registers. Uses is defined as for using non-operand registers and Defs is defined as for modifying non-operand registers. For example, for compare and compare with carry instructions, is my understanding correct that the instructions should be defined as described below? Considering that the carry flag is part of the status
2020 Feb 07
2
LLVM Backend Legalize Phase
Hello Sebastien, Thank you very much for the clarification. This would greatly help us in our development. I have noticed that setOperationAction(Expand) does not always work, for these cases, does it automatically mean that setOperationAction(Custom) should be used or not necessarily? Currently, we perform a pseudo instruction instead of setting it to custom. For example in the case of a
2020 Feb 18
2
Function Return Legalization
Hi llvm-dev, >> The CopyFromReg->CopyToReg->CopyFromReg sequence doesn’t have the chains set correctly: the second CopyFromReg’s input chain isn’t connected to the CopyToReg’s output chain. (This appears to be the same problem in both graphs.) The DAG mentioned was generated by the SelectionDAGBuilder and as much as possible, we only modify the files within our target so I tried
2020 Feb 12
3
Function Return Legalization
Hi All, In the target we are implementing, function return for i64 and f64 types has a different processing. For types i8 to i32, and f32, the return values are stored in their designated return registers (like how other targets does it). For i64 and f64 types, in the function call, after pushing the function parameters into the stack, the address of the allocated return memory space is
2020 Feb 14
2
Function Return Legalization
Hi, After removing support for the i64 type in the *CallingConv.td, sret-demotion is performed and we now have a store<(store 8, align 1)> DAG node being generated. Please refer to the attached dag_funcret.pdf DAG visualization. My understanding is that, the second operand(CopyFromReg->Register %1, Register %0 back-up) in the store node is the memory location allocated for the i64 type
2020 Mar 02
4
RTLIB and Custom Library calls
Hello LLVM-Dev, Most of the processing for i64 and f64 types for our backend are emulation library calls. Some of the library calls are not defined in the RuntimeLibcalls.def Libcall enum so we have to define custom library calls. How is the ideal way of implementing the custom library calls? Providing us with a target backend having a similar functionality would also help us significantly. Say
2013 Sep 17
2
new with xcp 1.6 - iscsi raw configuration
Hi all, I have experience with XEN, but I just start making tests with XCP. My XEN installation uses iscsi disks in raw mode (i mean using phy:/... for vm definitions where the block device is an iscsi lun managed by the dom0). I''m reading citrix manuals and googling a lot but still i''m not sure about the way to make such a configuration. Any of you has a tutorial for that
2010 Jul 15
1
Problem installing rJava under FreeBSD
Hi there I am setting up a FreeBSD server for my research department at university, and one of my teachers needs specifically R modules like tm, RWeka, rJava and the like. I have installed FreeBSD 8.0/i386 and applied the relevant security patches as well as the native FreeBSD JDK 1.6 with its latest patchset. I have installed R 2.11 and enabled Java support on it. Now, when trying to install
2020 Apr 17
1
Compare ISel
Good day LLVM-Dev, I hope all are in good health. We are currently implementing the compare operation for i64 type in our target. The main difference of the i64 type compare to lower integer types is that it performs a library call instead of generating a compare instruction. All is good until before ISelDAGToDAG class. We have observed that the difference in a compare operation for i32 and