similar to: Questions on ifconversion and predication

Displaying 20 results from an estimated 300 matches similar to: "Questions on ifconversion and predication"

2020 Sep 15
1
how does setMemory work?
Hi guys, I used setMemory in order to dynamically change guest's memory on QEMU-KVM. As expected, memory(total, free, available) in the guest was really changed, but after a few seconds, it automatically reverted to its initial memory. So, setMemory changes the guest's memory temporarily? Thanks.
2017 Jan 10
2
[PATCHish] IfConversion; lost edges for some diamonds
On Tue, Jan 10, 2017 at 2:31 AM, Peter A Jonsson <pj at sics.se> wrote: > Hi Kyle, > > my apologies for mailing you directly but it seems new user creation is > disabled on the llvm bugzilla. > > We sometime lose edges during IfConversion of diamonds and it’s not > obvious how to reproduce on an upstream target. The documentation for > HasFallThrough says *may*
2020 May 17
2
Question about the order of predecessors in LoopVectorizer with VPlanNatviePath
Hi All, I have got one domination error after running LoopVectorizer with VPlanNatviePath. Let's see simple IR snippet after loop vectorization with VPlanNatviePath. vector.body: ... br label %for.body10.preheader67 for.body10.preheader67: ; preds = %for.cond.cleanup972, %vector.body %vec.phi = phi <4 x i64> [ zeroinitializer, %for.cond.cleanup972 ], [ %8,
2014 Feb 12
2
[LLVMdev] ifconversion before register allocation
Hi all, I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering
2014 Jun 16
2
[LLVMdev] Machine level IfConversion for ARM
Hi All, How can I run the IfConversion pass in JIT to optimize my code for ARM as a Target Architecture? -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html Sent from the LLVM - Dev mailing list archive at Nabble.com.
2019 Nov 27
2
Optimization Record
I want to know all the optimization applied by the passes. I found two options in clang 1. -fsave-optimization-record 2. -Rpass-analysis=... However, they have nothing to do with the interaction btw IR files(.ll) Is there any tool that records all optimizations on IR file? -------------- next part -------------- An HTML attachment was scrubbed... URL:
2017 Oct 11
2
{ARM} IfConversion does not detect BX instruction as a branch
On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to
2014 Feb 18
2
Re: event-test.py cannot detects domain shutdown
2014년 2월 11일 오후 10:00에 Eric Blake <eblake@redhat.com> 작성: On 02/11/2014 12:20 AM, Kim Larry wrote: libvirtd version is 1.1.4 and using Xen for hypervisor. I'm not as familiar with the xen hypervisor as with qemu; it may just be the case that no one has coded the xen driver to send a shutdown event. At any rate, I can confirm that with the qemu driver, shutdown events are delivered. It
2016 Mar 29
0
IfConversion and representation of predicates
Hello, I have a few questions about applying the IfConversion pass to my out-of-tree target. (1) Is it true that the IfConversion pass may only run after register allocation? I often encounter this bad scenario, and I think it could be entirely avoided if IfConversion ran before register allocation: the block-to-be-predicated contains load-immediate (LI) instructions. The LI instructions
2013 Feb 06
0
[LLVMdev] Incorrect Simple pattern matching in lib/CodeGen/IfConversion.cpp
Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on
2012 Nov 01
0
[LLVMdev] : Predication on SIMD architectures and LLVM
On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we
2012 Oct 31
3
[LLVMdev] : Predication on SIMD architectures and LLVM
Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this
2019 Nov 06
2
Alias analysis only throwing mayAlias for something that seems should be identifiable as mustAlias
I have a global 2-D array ARRAY[N][M] and I am accessing it inside the for loop like this: for (i...) for (j ...) ARRAY[i][j] ... So nothing really weird is happening. If I look at the generated IR, it is also fairly straight forward. @ARRAY0 = dso_local global [32 x [32 x i32]] zeroinitializer, section ".slow_mem", align 32, !dbg !84 ... %45 = getelementptr inbounds [32 x [32 x
2019 Sep 20
2
About detailed rule of fastcall
Hello. I'm trying to understand how fastcall works. As far as I know, first two integer type arguments are passed in ecx and edx. I tested several test, but the result was different from what I expected #1 typedef struct _data_t { int d; } data_t; void __attribute__((fastcall)) test_suuu(data_t s, unsigned int a, unsigned int b, unsigned int c); unsigned int a is passed
2013 Apr 10
3
[LLVMdev] If Conversion and predicated returns
Evan, et al., I've come across a small issue when using the if conversion pass in PPC to generate conditional returns. Here's a small example: ** Before if conversion ** BB#0: derived from LLVM BB %entry %R3<def> = LI 0 %CR0<def> = CMPLWI %R3, 0 BCC 68, %CR0, <BB#3> Successors according to CFG: BB#3(16) BB#1(16) BB#1: derived from LLVM BB
2019 Jun 28
2
Conflicts with custom passes
You are right. Thanks! I fixed that one as well as some other issues. I built LLVM-8 with Debug + no-rtti. But it now has the following error: Stack dump: 0. Program arguments: clang-8 -cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -disable-free -main-file-name time-1.7.c -mrelocation-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases
2013 Jul 01
0
[LLVMdev] IfConversion non-recursive patch.
Hi. On our system we have a problems with recursive IfConversion algorithm. Here is the patch for making it loop-based. Or do I need to send it to some other mail-list? -- Best regards, Andrew Zhogin. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130701/f526e1f0/attachment.html> -------------- next
2011 Nov 02
0
[LLVMdev] ifconversion following br_cc instructions
Hi, I am trying to implement support for an if-conversion pass in a backend for the ADRES CGRA architecture. >From studying the existing IfConversion pass, I observed the following: - The PredicateInstruction method is meant to insert guards into conditional instructions. - This method assumes that one will be able to get the predicate from the conditional branch instruction on which
2014 Jun 18
2
[LLVMdev] Machine level IfConversion for ARM
I need to do some analysis, in which I have to selectively convert IFs. I am trying to find a way to call this optimization pass from the JIT code, thus I can decide which branches to convert and which to keep. Apparently I cannot do this using a pass manager. -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513p69622.html Sent from the