similar to: questionabout loop rotation

Hello, I'd be interested in knowing which pass performs loop inversion, i.e. transforms while loop into do/while wrapped with if. So, it's pretty easy to understand concept, http://en.wikipedia.org/wiki/Loop_inversion provides description of how its done and motivation, googling gives several relevant references, i.e. it's pretty settled term. I also see this transform to be actually

hi, I had an implementation of loop-rotation that peels the loop such that each conditional is executed at least once. https://reviews.llvm.org/D22630 This helps with LICM when instructions inside a conditional is loop invariant. The patch has decent number of test cases. All the requested comments were addressed at that time. I'm happy to rebase and put the patch again. -Aditya

Hi Stefanos, Thanks for your comments. I added both as reviewer. > One question though. Are you sure that this: > This helps with LICM when instructions inside a conditional is loop invariant  > is not achieved with the current LoopRotate pass? Because AFAIK, it does. Basically it inserts > a guard (that branches to the preheader) and then passes like LICM hoist invariant

Hello, I only recently started to look at LLVM assembly generated by Clang, and one of the first thing I saw was like: define i32 @foo(i32 %a, i32 %b) nounwind { %1 = tail call i32 @bar(i32 %a) nounwind %2 = icmp eq i32 %1, 0 br i1 %2, label %5, label %3 ; <label>:3 ; preds = %0 %4 = add nsw i32 %b, %a br label %7 I wondered what ";

On Mon, May 13, 2013 at 5:31 PM, Paul Sokolovsky <pmiscml at gmail.com> wrote: > Hello, > > I only recently started to look at LLVM assembly generated by Clang, > and one of the first thing I saw was like: > > define i32 @foo(i32 %a, i32 %b) nounwind { > %1 = tail call i32 @bar(i32 %a) nounwind > %2 = icmp eq i32 %1, 0 > br i1 %2, label %5, label %3 >

Hello, I'm trying to understand how fitting source integer type width into target machine register width happens. My reading on LLVM codegeneration topics (few megabytes) so far didn't have this topic mentioned explicitly. As an example, how %1 = add nsw i32 %b, %a gets compiled into msp430 (16bit CPU) assembly as: add.w r13, r15 addc.w r12, r14 Using -print-before-all

Hello, LLVM provides several ways to visual IR structure straight in its core - Function::viewCFG() to render control flow graph, then -view-* options to llc to render various stages of transforming to machine code. However, I wasn't able to find a way to render complete DAG visualization of normal IR - which besides CFG would also show dataflow (and other flows, if any). What people use to

Hello, On Fri, 22 Feb 2013 16:50:39 +0400 Anton Korobeynikov <anton at korobeynikov.info> wrote: > Hello > > > I'm trying to understand how fitting source integer type width into > > target machine register width happens. My reading on LLVM > > codegeneration topics (few megabytes) so far didn't have this topic > > mentioned explicitly. > This is

Hi, Aditya, I took a look but I was hoping for a simpler example. And something that is more "usual". As Florian mentioned, these branches are on undefs. But thank you. Best, Stefanos Στις Δευ, 23 Μαρ 2020 στις 1:16 μ.μ., ο/η Florian Hahn < florian_hahn at apple.com> έγραψε: > > > > On Mar 21, 2020, at 23:13, Aditya K via llvm-dev < > llvm-dev at

Hello, On Sun, 24 Feb 2013 19:15:27 +0100 Sebastian Dreßler <dressler at zib.de> wrote: [] > For a project involving a tree data structure, we created a graph for > representing IR for further analysis. I attached an excerpt of such a > graph to give you an idea. If it helps, we will see how to proceed ;) Well, after grepping LLVM source for apparent lack of it and googling for

> My server is equipped with a serial console which i now got > fully working under Xen. However it was not clear to me after > reading the documentation point 2.4.2 (Serial Console) that > the ttyS0 device would be provided by Xen and therefore i > need to remove the serial port driver from my linux kernel. I > therefore suggest adding a notice about that. > >

Hi LLVM-ers, I try to develop my custom dynamic data dependence tool (focusing on nested loops), currently I can successfully get the trace including load/store address, loop information, etc. However, when I try to analyze dynamic data dependence based on the pairwise method described in [1], the load/store for iteration variables may interfere my analysis (I only care about the load/store for

Dear Dibyendu, Thanks for your response. :-) > If you are looking for only dependences which are inter-iteration (dependence distance != 0 ) you can do a post-pass on the ld/st addresses collected Yes, I am more interested in inter-iteration dependence. Could you provide more information or some links on post-pass approach? I have no idea on your method. :-) > eliminate such

Dear Dibyendu and Mobi, Thanks for your help! :-) I finally figure it out. The solution is really simple. I just need to generate a new bitcode file with the following command: ----- opt -mem2reg -indvars test1.bc -o test2.bc ----- Then the load/store for induction variables will be removed and replaced by PHI instructions and all remaining load/store instructions are those I am interested in. I

Hi, On 02/24/2013 06:39 PM, Paul Sokolovsky wrote: > Hello, > > LLVM provides several ways to visual IR structure straight in its core - > Function::viewCFG() to render control flow graph, then -view-* options > to llc to render various stages of transforming to machine code. > However, I wasn't able to find a way to render complete DAG > visualization of normal IR -

Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a

Hi Paul, On 02/24/2013 08:54 PM, Paul Sokolovsky wrote: > Hello, > > On Sun, 24 Feb 2013 19:15:27 +0100 > Sebastian Dreßler <dressler at zib.de> wrote: > > [] > >> For a project involving a tree data structure, we created a graph for >> representing IR for further analysis. I attached an excerpt of such a >> graph to give you an idea. If it helps,

Hi, there I am writing an backend, and I met a problem. We don't have load/store instructions for vector predicate registers(vpr for short). The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr. vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations. A vr has 512 bits, and

You can get the name of a variable by using the method getName() of llvm::Value. However it returns a blank string if the variable is a numbered variable, such as %11. How can I make it return %11 in such case. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130222/d6d434e8/attachment.html>

Hello > I'm trying to understand how fitting source integer type width into > target machine register width happens. My reading on LLVM > codegeneration topics (few megabytes) so far didn't have this topic > mentioned explicitly. This is done during DAG Legalization phase. The operation is splitted into two (ADD + ADDC / ADDE). These DAG nodes are later matches during