similar to: How to add new AVR targets?

Thanks! The new are of xmega3 architecture, which is already included. So this should be simple. Where is the information about ISR-vector table, SRAM addresses and so on stored? -- Wilhelm Am 04.03.20 um 11:03 schrieb Dylan McKay: > Hey Wilhelm, > > This should be possible by editing the 'AVRDevices.td' [1]TableGen > definitions to add an entry for the newer chip types.

Am 04.03.20 um 11:16 schrieb Dylan McKay: > > The new are of xmega3 architecture, which is already included. So this > should be simple. > > Where is the information about ISR-vector table, SRAM addresses and so > on stored? > > > At the moment, this is not implemented in LLVM; these details are left > to the frontend. Clang/compiler-rt does not

Hi Dylan, the following code volatile uint8_t v1; volatile uint8_t v2; __attribute__((interrupt)) void __vector_21(void) { v2 = v1; } produces in C mode: 00000092 <__vector_21>: 92: 80 91 61 00 lds r24, 0x0061 ; 0x800061 <v1> 96: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <__data_end> 9a: 08 95 ret and in C++ mode: 00000074

Hey Wilhelm, That's a bug, the "interrupt" attribute is not being recognized by the backend. I have fixed it in https://github.com/llvm/llvm-project/commit/339b34266c1b54a9b5ff2f83cfb1da9cd8c9d90a Pull the latest LLVM and it should be fixed. On Tue, Mar 31, 2020 at 8:00 AM Wilhelm Meier <wilhelm.meier at hs-kl.de> wrote: > Hi Dylan, > > I used the following

Am 04.03.20 um 13:28 schrieb Dylan McKay: > > * *The C/C++ function needs to be declared with either the calling > convention avr-interrupt or avr-non-blocking-interrupt.* Skipping > this step will cause regular ret instructions to be emitted for > return-from-subroutine, instead of the required reti for interrupt > handlers. ISRs also have stricter

Hey Wilhelm, Could you post the LLVM IR generated from your C++ file? This can be achieved with 'clang -S -emit-llvm' Cheers On Sat, Mar 28, 2020 at 6:36 PM Wilhelm Meier <wilhelm.meier at hs-kl.de> wrote: > Answering partly to myself there was a extern "C" missing. > > But the register pushes ans reti are still missing. > > Whats wrong? > > Am

Is there anything I can do about it? BTW: gcc is loosing the AVR backend, so I would assume, there will be a greater interest to this in llvm compared to the past. Thanks, Wilhelm Am 03.04.20 um 15:09 schrieb Wilhelm Meier via llvm-dev: > Should I create an issue in bugzilla for this? Just to be reminded ... > > Am 31.03.20 um 09:34 schrieb Wilhelm Meier via llvm-dev: >> Hi

Hi Dylan, looks ok now. One thing: the ISR is now: __vector_21: ; @__vector_21 __vector_21$local: sei push r0 push r1 in r0, 63 push r0 clr r0 push r24 lds r24, v1 sts v2, r24 pop r24 pop r0 out 63, r0 pop r1 pop r0 reti There are unneccessary push/pops of r1 and r0 too, since the clr is useless ... GCC had the same

Hi, I am trying to do a backend to a very simple microcontroller. I have some questions. 1) I have instruction which do "r1 <- r1 op r2", from what I have ssen I must declare them like: let isTwoAddress = 1 in def ADD : FopRR< 0b01010, (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), "ADD $sX, $sY"), [(set

Hi, The AVRDevice.td of the AVR target seems too old, some devices like at90s have already been End-Of-Live, and some devices such as AVR DA family are not included. It is possible to make this TD file follow current microchips device list definition ? I am glad to take this work. 1. remove EOL devices 2. add new production devices Ben -------------- next part -------------- An HTML

I just detected, that det() is not working on complex matrices any more, due to the fix to the bug reports noted above. I am not happy with this, as determinants are perfectly usable on complex matrices. AFAIUI the bugs resulted from less than optimal behaviour of qr() in certain cases. IMHO this is due to the unhappy decision to use a default for parameter tol to decide whether the the

hello all... i am trying to install r v2.0.1 on my suse 9.2 pro box... when i run configure, i get the following error: checking how to get verbose linking output from g77... configure: WARNING: compilation failed checking for Fortran libraries of g77... checking for dummy main to link with Fortran libraries... none checking for Fortran name-mangling scheme... configure: error:

How is the llvm-avr backend integration going ? Will it be functional ( experimental ) in the 3.8 release ? Will Clang recognize options for avr ? thanks. Allen -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151218/be23dc42/attachment.html>

Hello all, I am loading a data frame, fitting a model, getting diagnostic plots and they are flagging a couple of observations as problematic. Fair enough, and I want re-fit without them. After I delete an offending row (identified by one of the diagnostic plots), something like data = data[-3,]; then R will no longer print the contents of the data frame; it tells me it is a data frame

Hi, Just a small patch for user of tablegen.vim I added support for: - defm and multiclass - imbricatable multiline C style comment - FIXME/TODO highlight in comment - binary and hexadecimal number - code using [{ }] is no highlighted as special (perhaps not the best choice) If someone has comment or idea to enhance, I will be happy to hear it. Regards, -- Cédric Ps: Is there somewhere a

To those interested in AVR backend additions to LLVM, the LLVM review tools "Phabricator" ( don't ask me to say that 3 times fast ), allows easy searching. Go to http://reviews.llvm.org/ and type in AVR in the search entry. This will give you a list of the commits, and resolutions. From my understanding ( NO Expert ), a large part of the skeleton code has been added. The leave

Hi, There was a thread a few days ago about the expectations for experimental targets. At the moment, the only experimental target is AVR. It's been in the tree for a long time now, and generally seems well-behaved. Should we just make it a normal target? Nico -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, I am not exactly sure what causes your error. But if you have a reduced test case we can try looking at it. Thanks, Arushi Hello, i wrote a little pass. It tries to identify every call- / invoke-instruction recursively and calls computeCalleeCallerMapping for each. The sample program just creates a vector of integer and adds an element to it. Do you know what's wrong? Best,

Hi All, For quite some time there's been a side project for developing an AVR back end for LLVM: http://sourceforge.net/projects/avr-llvm/ What is required from us to be able to add this work to the LLVM repo? And when do you think would be a good time for us to do that? If this is located somewhere in the docs and I've missed it, pointers would certainly be appreciated. Thanks, Eric

Hi, I have been looking through all packages but I cannot find a routine for LAD-regression (L1-norm-regression). Is there none? Willi