similar to: New atomic handling status

Displaying 20 results from an estimated 11000 matches similar to: "New atomic handling status"

2020 Feb 24
2
New atomic handling status
> On Jan 22, 2020, at 19:49, Philip Reames <listmail at philipreames.com> wrote: > > In short, I hit a major stumbling block. I hadn't account for the fact that some atomic stores dependent on element type (float vs int for instance) for legality. I think this qualifies as a target/infrastructure bug. It should always be legal to cast the FP atomic load/store to integer. This
2019 Feb 02
3
GlobalISEL, and MachineMemOperands?
Looking through the X86 GlobalISEL code for selecting loads and stores, I'm not seeing the creation of the MachineMemOperands I'd expect to see and do see being generated by SelectionDAG.  Is this simply an oversight, or is there some aspect of the new design which pushes us away from MMOs? Various parts of the machine instruction level optimization passes use the existence and
2018 Jul 31
2
GlobalISel design update and goals
> On 30 Jul 2018, at 16:04, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Amara, > > Thanks for sharing the plan going forward. > > Inlined a couple of comments. > > 2018-07-30 7:01 GMT-07:00 Amara Emerson via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>>: >> Hi all, >> >>
2018 Aug 03
2
GlobalISel design update and goals
> On 2 Aug 2018, at 14:50, Quentin Colombet <quentin.colombet at gmail.com> wrote: > > Hi Daniel, > > 2018-07-31 8:40 GMT-07:00 Daniel Sanders <daniel_l_sanders at apple.com>: >> >> >> On 30 Jul 2018, at 16:04, Quentin Colombet via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >> >> Hi Amara, >> >> Thanks for
2018 Jul 30
9
GlobalISel design update and goals
Hi all, Over the past few months we’ve been doing work on the foundations for the next stages of GlobalISel development. In terms of changes from this time last year, the IR translator, the legalizer, and instruction selector have seen moderate to major changes. The most significant of these was the change to the legalizer API, allowing targets to use predicates to express legality, which gives
2017 Jan 17
2
RFC: Building GlobalISel by default
Hi Michael, > On Jan 13, 2017, at 6:38 PM, Michael Kuperstein <mkuper at google.com> wrote: > > As a person not developing on GlobalISel, I can already play with it by setting the flag. ;-) > > The main (and huge) benefit I see is that it will get tested by default. I agree. > So, I think it's mainly a question of maturity - if my (non-GlobalISel) change breaks
2017 Jan 14
4
RFC: Building GlobalISel by default
> On Jan 14, 2017, at 4:57 AM, Renato Golin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 14 January 2017 at 01:54, Quentin Colombet via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Now, four backends (if I am counting right: X86, ARM, AArch64, AMDGPU) are working on bringing-up GlobalISel, I’d like to switch the default of the LLVM_BUILD_GLOBAL_ISEL
2019 Oct 29
2
What rebuilds the sphinx documentation at llvm.org?
Hi All, I've been working on some documentation changes for GlobalISel and it looks like they aren't being reflected on llvm.org <http://llvm.org/>. In particular, the change I landed on the 25th Oct (https://github.com/llvm/llvm-project/commit/feab0334f57d) hasn't appeared yet. This commit changed the 'Global Instruction Selection' link at
2017 Mar 29
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi, GlobalISel, the SelectionDAG replacement, has come a long way since initially discussed on the mailing list and its last discussion at the EuroLLVM BoF (https://etherpad.net/p/GlobalISel <https://etherpad.net/p/GlobalISel>). We believe we are close to the point of enabling it by default on AArch64 at O0. We now would like to enlist your help to get there. *** Quick Status *** On iOS
2017 Jul 06
2
[RFC][GlobalISel] Making GlobalISel non-optional in the build
Hi, I would like to get rid of the logic around disabling GlobalISel from the build. *** Context *** So far, GlobalISel has been this framework built up on the side for about two years. Now, we are close to a point where having it being optional impedes our ability to implement the right things. For instance, checks that would fit naturally in the MachineVerifier are directly done during the
2017 Jan 14
13
RFC: Building GlobalISel by default
Hi all, Now, four backends (if I am counting right: X86, ARM, AArch64, AMDGPU) are working on bringing-up GlobalISel, I’d like to switch the default of the LLVM_BUILD_GLOBAL_ISEL variable in CMake, such that the framework gets built by default. ** Impact of Flipping the Switch ** * Upsides * For people developing on GlobalISel, it will: - Simplify the CMake command to type :) - Build/Test
2018 Dec 21
2
[OpenMP][AArch64][GlobalISel] AArch64 OMPT tests failing
Curious. I removed -fno-experimental-isel and all of the tests *except* control_tool.c passed. I would have expected all of them to pass if blockaddress works. I'll try to look at some asm and see what's going on. -David Jonas Hahnfeld <hahnjo at hahnjo.de> writes: > Hi David, > > I was the one who originally added the flag to fix failures
2018 Dec 20
2
[OpenMP][AArch64][GlobalISel] AArch64 OMPT tests failing
We're seeing OMPT tests fail on AArch64: libomp :: ompt/misc/control_tool.c libomp :: ompt/synchronization/master.c libomp :: ompt/synchronization/taskwait.c The failure mode is similar for all of them: openmp/runtime/test/ompt/misc/control_tool.c:26:17: error: CHECK-NEXT: expected string not found in input // CHECK-NEXT: {{^}}[[MASTER_ID]]:
2020 Apr 06
4
[GlobalISel] Extended inline assembler support
Hi! So far, GlobalISel only supports very basic inline assembler constructs (no input/output operands, only simple memory clobbers). In [0], I'm adding support for generic register, immediate, memory and clobber constraints. The code is more or less a direct port from the handling in SelectionDAGBuilder. Before moving on with target specific constraints, I'd like to discuss the
2017 May 09
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin, On Tue, May 9, 2017 at 11:47 AM Quentin Colombet via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi Kristof, > > On May 9, 2017, at 3:41 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > > Great Quentin :). > > I've rerun the benchmarks comparing "-O0 -g" with "-O0 -g -mllvm > -global-isel -mllvm
2019 Jul 24
2
About a new porting of GlobalIsel for RISCV
Hi, I would like to start a new porting of GlobalIsel for RISCV. An initial patch about GlobalIsel infrastructure for RISCV was ready now: https://reviews.llvm.org/D65219 There is another porting patch https://reviews.llvm.org/D41653 posted by Leslie Zhai at the end of 2017. I have checked with Leslie about the status of this patch.He has stopped developing it since some questions need be
2017 Jul 02
2
[GlobalISel] G_LOAD/G_STORE i64/f64 handling
Hi all, I am working on enabling X86 using GLobalIsel framework. I have 32bit platform + float/double configuration (-mtriple=i386-linux-gnu -mattr=+sse2 ) load i64, i64* %p1 - illegal, require narrowScalar action load double, double * %p1 - legal What is the best approach to Legalize this case ? Should I mark G_LOAD/G_STORE s64 as Custom?
2017 May 09
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Great Quentin :). I've rerun the benchmarks comparing "-O0 -g" with "-O0 -g -mllvm -global-isel -mllvm -global-isel-abort=2" on r302453, on AArch64 Cortex-A57. I indeed see almost no moves between GPR and FPR registers anymore (see details below for where I still see some). On geomean, I see 13% slow down (down from 17% on my previous run). On geomean, code size increase
2017 Jan 19
3
RFC: Building GlobalISel by default
> On Jan 19, 2017, at 11:59 AM, Quentin Colombet <qcolombet at apple.com> wrote: > > Hi all, > > Trying to summarize the concerns along side my answers but I believe we are good to do the switch to build GlobalISel by default. In particular, Renato and I exchanged offline and he tried doing the switch on some of the bots he maintained and did not see any overhead/problem for
2017 Jun 21
4
[SPIR-V] SPIR-V in LLVM
On 06/20/2017 05:41 PM, Neil Hickey wrote: > Hi all, I'd like to kick this discussion off again, and summarise the points that have been expressed so far. > > Firstly, as a member of Khronos, I'd like to state that this would be a very interesting development. > Hi Neil, I am very interested in having a good LLVM IR -> SPIR-V solution, and I think it's great that