similar to: Encode target-abi into LLVM bitcode for LTO.

David Blaikie <dblaikie at gmail.com> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per file in a compilation and resolve > correctly when one object file is built with one ABI and another object > file is built with a different ABI (that seems to be antithetical to the > concept of "ABI" Though) - then it should be a subtarget feature. > > ABI is

> On Jan 6, 2020, at 14:29, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > On Mon, Jan 6, 2020 at 5:58 AM Zakk <zakk0610 at gmail.com <mailto:zakk0610 at gmail.com>> wrote: > > > David Blaikie <dblaikie at gmail.com <mailto:dblaikie at gmail.com>> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per

> On Jan 7, 2020, at 13:57, David Blaikie <dblaikie at gmail.com> wrote: > > > > On Mon, Jan 6, 2020 at 6:05 PM Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > > >> On Jan 6, 2020, at 14:29, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:

On Tue, Jan 7, 2020 at 5:27 PM Eric Christopher <echristo at gmail.com> wrote: > > > On Tue, Jan 7, 2020 at 3:18 PM Daniel Sanders via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Jan 7, 2020, at 13:57, David Blaikie <dblaikie at gmail.com> wrote: >> >> >> >> On Mon, Jan 6, 2020 at 6:05 PM Daniel Sanders

Right. I think that's what we ended up doing rather than a more general attribute on the module itself. *shrugs* Probably ok? I'd probably prefer not to have to have target code to do the evaluation if possible, but everything is weird and an edge case - mips abis more than some :) -eric On Wed, Jan 8, 2020 at 8:58 AM David Blaikie <dblaikie at gmail.com> wrote: > Oh, I should

David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> 於 2020年1月11日 週六 上午2:03寫道： > Ah, OK - thanks for walking me through that. > > Fair enough, I think I understand the issue/tradeoff now - and that the > other module level metadata don't currently influence the target > configuration at this level? > > I'm not sure, I only know that the target-abi is decided

I also work on the RISC-V backend, and have been doing a little work on the ELF psABI document for RISC-V. I agree that, conceptually, the psABI choice should be in the module metadata. Zakk, however, has discovered a phase ordering issue within LLVM that relates to this approach. The phase ordering problem is that the LTO backend is currently setup without interrogating the current module for

David Blaikie <dblaikie at gmail.com> 於 2020年1月14日 週二 上午2:15寫道： > > > On Mon, Jan 13, 2020 at 6:12 AM Zakk <zakk0610 at gmail.com> wrote: > >> >> >> David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> 於 2020年1月11日 週六 >> 上午2:03寫道： >> >>> Ah, OK - thanks for walking me through that. >>> >>> Fair enough, I

On Mon, Jan 20, 2020 at 8:05 AM Sam Elliott via llvm-dev < llvm-dev at lists.llvm.org> wrote: > To follow up on this issue: > > Our plan is still to encode `target-abi` into the module flags for RISC-V > LLVM IR modules. As was pointed out earlier in this thread, the function > lowering in Clang is slightly different for the ABIs which support hardware > floating point.

On Mon, Jan 27, 2020 at 3:04 PM Eric Christopher <echristo at gmail.com> wrote: > > > On Mon, Jan 27, 2020 at 2:56 PM David Blaikie via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Mon, Jan 20, 2020 at 8:05 AM Sam Elliott via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> To follow up on this issue:

Hello LLVM, I'd like to check TSFlags in my AsmBackend code. However AsmBackend objects don't have a reference to MCInstrInfo, which is the only way I've seen to reach TSFlags. A quickie grep shows that none of the existing targets check TSFlags in their AsmBackends. Is there any reason I shouldn't check TSFlags in AsmBackend? If not, what's the best way to go about it?

Hello, I'm working on an LLVM backend for an experimental microprocessor. Work is going on nicely, and I've until now found the answer to all my questions directly in the LLVM source code, or in the documentation. However, I'm having problems with the AsmBackend class and the handling of fixups. The processor I'm working with has a single conditional branch instruction, JCC,

Eli, Yes, SubtargetInfo is more of a container of convenience since it is available to all the assemblers. Working with the current framework it seemed the least disruptive. I'll describe the problem again. The Mips ABI for better or worse, uses the ELF headers e_flags extensively. The most pressing issue is the need to post the relocation model such as PIC, CPIC or non-shared. The object

Hi ! > Sorry I missed responding to this email sooner. No problem, I was not in a hurry. :) > The approximate approach I had in mind sounds like what you describe, Ok Cool ! > I have been meaning to do this, but won't have time for a couple weeks I suspect. So I will give it a try. :) I was able to quickly hack a JITObjectWriter and I am able to execute simple functions (with

Hi all developers, I'm changing compiler from gcc to llvm on a RISCV target now. but I found in some case the assembly code generated by llvm is much more than gcc. It cause my program's performance about 40% decrease. The flowing is a simple test code. It shows the problem. We can see than gcc prefer to use pointer to iterate the array, but llvm perfere to use index to iterate

Hi Matt, Awesome! This is excellent progress, and it is great to see someone working on this. High level comments: (1) The order of patches is odd, to me. It would be great to start by adding the AsmParser support, then the MCStreamer support, so that we can have test cases in the 'llvm-mc cat' mode, where it just parses and prints out again. On 0001: - What is hasRelocationAddend? It

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

On Fri, Dec 14, 2012 at 1:03 PM, Carter, Jack <jcarter at mips.com> wrote: > Eli, > > This is the kind of feedback I want. I believe I have to add to the base class so it should be generally useful. I can see string being better for the value. I still am enamoured with an enumeration for the tab though: int->string. How would that be a limitation? > I guess that's fine,

I was misconstrued as having insulted Minister Mentor Lee Kuan Yew. My words were twisted and misinterpreted and I feel that there is a need to explain myself and set the record straight. [b]What really happened[/b] It was sometime in Aug/Sep in the year 2009. The setting was in the Tampines Central office of Asiasoft Online Pte Ltd. I was having a ***verbal*** conversation with Melvin Lee,