similar to: [Machine IR] Analyzing Assembly Source Code in MIR passes

Llvm-mctoll will raise a binary back to LLVM IR. Not exactly what you want but it might be something you can leverage. https://github.com/microsoft/llvm-mctoll On Mon, Nov 25, 2019 at 1:19 PM Nicolai Hähnle via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On Thu, Nov 21, 2019 at 3:37 AM Lele Ma via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > My goal is to write

Hi All, A self-follow up and rephrase of my previous question with updated subject: What I want to do is to analyze hand-written assembly code with 'full details' where semantics of each instruction can be known in LLVM passes. Many of such instructions have no corresponding counterparts in IR/MIR forms, such as 'syscall' 'iret', etc. At MC level, such assembly code can

> On May 26, 2015, at 1:37 PM, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > >> >> On 2015-May-26, at 09:46, Alex L <arphaman at gmail.com> wrote: >> >> Hi all, >> >> The CodeGen library is a big bag of interdependent bits. This caused >> a circular dependency in the MIR serialization commit (r237954), which got >>

+1. Could those two be subdirectories of one “Machine-Related-Stuff” directory? E.g., MachineStuff/IR MachineStuff/CodeGen Where MachineStuff is something meaningful :). That way, they keep a logic bound, more formal than the naming convention. My 2c. Q. > On May 26, 2015, at 9:28 PM, Chris Lattner <clattner at apple.com> wrote: > > On May 26, 2015, at 1:46 PM, Owen Anderson

Hi all, The CodeGen library is a big bag of interdependent bits. This caused a circular dependency in the MIR serialization commit (r237954), which got reverted in r238007. I propose separating the machine IR out of CodeGen and into its own MIR library, living at lib/MIR. This touches every target but it's mostly a mechanical change that renames the header files, although a couple of

Dear LLVM developers, Just as LLVM IR can be read/write via persistent bitcode (*.bc *.ll) files, is there any similar implementation in LLVM to read/write Machine IR (MIR) via a persistent file? If not and I would like to add it (e.g. for ARM or RISC-V), could you direct me materials and/or LLVM source code modules where I should start with? Best Regards, Lele Ma -------------- next part

2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: > > On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com> wrote: > > > >> On Wed, May 27, 2015 at 8:15 AM Chris Lattner <clattner at apple.com> > wrote: > >>> On May 26, 2015, at 11:20 PM, Quentin Colombet <qcolombet at apple.com> > wrote:

> On 2015 May 27, at 14:01, Alex L <arphaman at gmail.com> wrote: > > > > 2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: > > On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com> wrote: > > > >> On Wed, May 27, 2015 at 8:15 AM Chris Lattner <clattner at apple.com> wrote: > >>>

> On May 27, 2015, at 2:18 PM, Duncan P. N. Exon Smith <dexonsmith at apple.com> wrote: > > >> On 2015 May 27, at 14:01, Alex L <arphaman at gmail.com> wrote: >> >> >> >> 2015-05-27 10:59 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: >>> On 2015 May 27, at 10:24, Chandler Carruth <chandlerc at google.com>

On Wed, May 27, 2015 at 8:15 AM Chris Lattner <clattner at apple.com> wrote: > On May 26, 2015, at 11:20 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > > +1. > > Could those two be subdirectories of one “Machine-Related-Stuff” directory? > E.g., > MachineStuff/IR > MachineStuff/CodeGen > > Where MachineStuff is something meaningful :). >

Hello Valentin, To generate a mir test case i think the process is to first create an IR file by passing '-S -emit-llvm' to clang, then you can feed that file into llc and use stop-before to get the mir just before the if-converter pass, eg: `llc -stop-before=if-converter -simplify-mir -o test.mir test.ll`. Also there is a MIR language reference: https://llvm.org/docs/MIRLangRef.html

Hello, I am trying to isolate an assertion failure in if-converter (on PPC) and I generated a textual debuglog with: ``` LLVM_ARGS=-print-before-all -print-module-scope -filter-print-funcs=japi1__require_7687 ``` and after splicing out the the MIR before the if-converter pass I would like to run `llc -march=ppc64le -run-pass=if-converter input.mir` so that I can start minimising the MIR. This

Thank you both! I was running into the issue that bugpoint was reducing my test-case into other failures and I hadn't managed yet to find the right point in the Julia pass pipeline to insert the module to reproduce the issue reliably from llc and that's why I started looking at using the MIR. I will go back at looking at the pass pipeline and the IR and get a reproducer that way!

Valentin, in terms of limitations as Sean pointed out, an important one is that .mir doesn't have MachineFunctionInfo which may result in failure on accesses to global variables due to use of register X2. The verifier considers it an undefined register. Also, it's probably easier to reduce test cases using bugpoint starting from an IR test case. With the code you provided, I get a

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

In our fork of LLVM we often need to reduce a crash testcase for a specific assertion. After writing lots of "only give me this specific assertion" scripts like the above I decided to write a script that automates all this for me: <https://github.com/CTSRD-CHERI/clang/blob/master/utils/creduce_crash_testcase.py>. (It's called creduce_crash_test.py but it will actually use

Hi all, After a recent upstream merge into our downstream sources we are suddenly encountering the freeze instruction in LLVM IR for div/rem pairs. This seems to be related to [1]. Our downstream target is GlobalISel only and unfortunately GlobalISel doesn't support this instruction yet, so most of our internal test-suite is now breaking due to GlobalISel not being able to translate this

I'm not sure if this helps, but here it is in case it does. I typically use bugpoint in a way as to keep the actual failure that I'm after. For example, with the test case you've pasted, I was looking for a specific assert. So I used bugpoint this way: $ cat reduceme.sh #!/bin/bash llc -filetype=obj $1 2>&1 | grep 'Cannot lower calls with arbitrary operand bundles'

In light (pun not intended) of the announcement here https://wiki.ubuntu.com/MirSpec what does this mean for LightDM being a viable free desktop display manager. The diagram shows the system compositor as being launched by LightDM in much the same way X is, and the plan looks very much like what we would do for Wayland. Is MIR going to be a hard dependency? Is Wayland support going to be dropped

I am confused about the rules for when upper and lower case letters should be used in MIR. As an example our downstream target has upper case letters in its sub-register indices and as a result we cannot import exported MIR without manually 'lower casing' it first which is obviously rather annoying. Looking in https://llvm.org/docs/MIRLangRef.html it is stated that instruction names are