similar to: Understanding targets

Hello Paul and Simon, (Sorry - I'm not sure about the social conventions in mailing lists) Both of your answers helped me a lot! So If I understand it correctly, Clang knows what 'mips1' and 'mips5' are - but can't generate code for it? Why is it like that? I actually have a more in general questions about processors... If this is the wrong place for it, please ignore it,

I'm cross-compiling for MIPS. The test-case is as simple as it can be: void foo() {} $clang -target mips64-octeon-linux -c -B path/to/cross/compiled/mips/assembler a.c And then I look at the object file: $ nm a.o 0000000000000020 t $tmp0 0000000000000000 T foo I would like to know what "$tmp0" is. Furthermore, if I pass -g to clang, I see a whole bunch of such symbols. Some of

We are trying to use LLVM (Clang as the C frontend) to generate code for 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 sslittle-na-sstrix platform. Can you advise what would be the right way to use the LLVM compiler infrastructure? The following is the one I used, but it appears that it produce the code in big-endian (and I wonder whether the calling convention is right.) To

My guess is he wants mips1 so that he doesn't have to worry about the patented mips instructions? At any rate, it will be a bit of work to enable a mips1 target and I doubt many people are interested, so it'll definitely be up to him to do the work. -eric On Fri, Apr 26, 2013 at 10:15 AM, Reed Kotler <rkotler at mips.com> wrote: > If you want to create a version for the mips1

It will produce little-endian code if you replace "mips" with "mipsel". 1. clang -ccc-host-triple mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -emit-llvm foo.c -o foo.ll 2. llc -march=mipsel -mcpu=4ke foo.ll -o foo.s (the -march option is redundant) If you do not specify the target cpu with -mcpu, by default it will generate code for Mips1, which has not been tested as

Hi LLVM developers, GCC[1] is able to use Loongson ISA[2] for instruction selection: $ cat hello.c #include <stdio.h> int main(int argc, char *argv[]) { printf("Hello World\n"); return 0; } $ gcc -O0 -S hello.c $ cat hello.s .file 1 "hello.c" .section .mdebug.abi64 .previous .nan legacy .gnu_attribute 4, 1 .abicalls

- my old email address. The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or

But then I should write // CHECK: something // SSE: something // SSE3: something With this feature it can be write // {{[A-Z0-9]+}} : something From: James Y Knight [mailto:jyknight at google.com] Sent: Thursday, May 26, 2016 5:53 PM To: Ehsan Amiri <ehsanamiri at gmail.com> Cc: Elena Lepilkina <Elena.Lepilkina at synopsys.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject:

Hi Everybody, I'm working a project which requires assembly code for mips1 architecture for simulation purpose. I checked the latest LLVM3.2 version and found that the backend has been removed. I tried to replace the MIPS backed in LLVM3.2 by the old one in LLVM2.9 (which contains mips1) and adjust some routines to get the backend compiled. However, when llc is used to generate the assembly,

On Thu, May 26, 2016 at 10:35 AM, Ehsan Amiri via llvm-dev < llvm-dev at lists.llvm.org> wrote: > 7. Wildcard for prefixes - If some statements should be checked > regardless prefix, it should be used //{{*}}, //{{*}}-NEXT, //{{*}}-SAME > and etc. > >> 8. Prefix with regular expressions - If statement should be >> checked if prefix matches some regular

If you want to create a version for the mips1 subtarget, going back in time will probably be a lot of work for you. If you want to modify the current version you might try the following: 1) Create a Mips1 predicate and use that to disable instruction patterns that match using non Mips1 instructions. 2) Use soft-float 3) You would need to reenable some commented out code used to implement

On 25 Jun 2014, at 12:58, James Molloy <james at jamesmolloy.co.uk> wrote: > This is one of the worst parts about the Clang CLI for cross compilation at the moment. I'd really like, if we're changing the CLI, to allow users to remove it. For example, if I specify -march=armv7-a, it *shouldn't* need me to put "-target arm" before it to work! One thing that I've

On 06/12/2015 07:12 PM, Daniel Sanders wrote: > > Hi, > > I'm afraid targeting a 64-bit CPU and the O32 ABI is completely broken > at the moment, it's one of the very long-standing issues I'm working > towards. The main problem is that a lot of the internals of the Mips > LLVM backend derive their behaviour from the target CPU rather than > the target ABI.

Full_Name: George N. White III Version: 1.9.0 OS: Irix 6.5.21m Submission from: (NULL) (142.176.61.212) R-1.9.0 built using the SGI MIPSPro compilers Installation directory: /usr/local C compiler: c99 -OPT:IEEE_NaN_inf=ON -mips4 -n32 -O3 -OPT:Olimit_opt=on C++ compiler: CC -OPT:IEEE_NaN_inf=ON -mips4 -n32 -O3 -OPT:Olimit_opt=on -LANG:std Fortran compiler:

Hello, I'm using clang on x86 cross build for mips, here is my main configure parameters llvm/configure \ --prefix=/usr \ --target=mipsel-unknown-linux-gnu \ --enable-targets=mips \ --enable-optimized \ --enable-shared \ --disable-assertions I want to build code for *mips3* with *o32* abi, but

On 06/16/2015 06:21 PM, Daniel Sanders wrote: > > > > the best I can suggest is to target mips2 and O32 > > > > It's not work for all, still get Assembler messages error on some > source files > > > > > Warning: float register should be even, was 7 > > Could you add –save-temps to the compiler command and send me the > command along with the

Hi there. I need some advise on how to configure NUT, if it is possible to do it. My UPS, a Compaq R3000 has three individual power segments. I want NUT to: When mains is interrupted. Shut down all serves immediately. When all servers are completely down, in sequence with time delay shut down two of the power segments. When batteries is about to be depleted shut down itself and the last power

Hi Matthijs, > Arnaud. >After some trial and error, i found out that the HP R3000 XR ups's we have >can be used with Network Ups Tools. >This using the bcmxcp driver. > >Note that in the code of this driver (line 1420) , the Baudrate is fixed to >9600 baud. >to connect to a serial HP R3000 XR ups one needs to change this to 19200 >baud. > >ideally, this should

Hi All, I put my Compaq R3000 UPS on NUT. Every once in a while the battery alarm light turns on, on the front of the UPS. Maybe once every couple of days or so. When that happens I get the following output in /var/log/messages: Sep 22 01:51:46 mail upscode2[90734]: Unknown response to UPDS: .20 MOUL1 Sep 22 01:51:46 mail upscode2[90734]: Unknown response to UPDS: 0119.20 MOIL1 Sep 22

Hello all, Does anyone know where I could turn to find out how to set up the NVIDIA driver to work properly on my Compaq Presario R3000? Thanks in advance, Phil