similar to: [AVR] [MSP430] Code gen improvements for 8 bit and 16 bit targets

On Wed, Nov 13, 2019 at 12:26 PM Joan Lluch via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi All, > > In relation to the subject of this message I got my first round of patches successfully reviewed and committed. As a matter of reference, they are the following: > > https://reviews.llvm.org/D69116 > https://reviews.llvm.org/D69120 >

As before, I'm not convinced that we want to allow target-based enable/disable in instcombine for performance. That undermines having a target-independent canonical form in the 1st place. It's not clear to me what the remaining motivating cases look like. If you could post those here or as bugs, I think you'd have a better chance of finding an answer. Let's take a minimal example

Hi All, While implementing a custom 16 bit target for academical and demonstration purposes, I unexpectedly found that LLVM was not really ready for 8 bit and 16 bit targets. Let me expose why. Target backends can be divided into two major categories, with essentially nothing in between: Type 1: The big 32 or 64 bit targets. Heavily pipelined with expensive branches, running at clock

For any of the examples shown below, if the logical equivalent using cmp + other IR instructions is no more than the number of IR instructions as the variant that uses shift, we should consider reversing the canonicalization. To make that happen, you would need to show that at least the minimal cases have codegen that is equal or better using the cmp form for at least a few in-tree targets. My

Hi all, I'm rappedly moving away from windows, but one of the last programs i need to run in windows is 'IAR Embedded Workbench (Kickstart Version)' I've tried to run it some time ago (i think about 2 months back) in wine, but it didn't work so well back then. I haven't tried it with newer versions since then. I need that program so i can program my msp430

Hi, Is there any implementation for MSP430 backend to LLVM ? Maybe at very early phase. (I did not found anything in google). I need this because mspgcc's support of newest TI's MCU seems very unstable. If there any project for MSP430, I'd better join it rather than develop the whole thing from scratch. --- Regards, Dmitry

Hello, Several people have expressed interest in using LLVM to target MSP430 microcontrollers. Anton wrote an MSP430 backend as an exercise, and some of the nastiest parts are done (thanks Anton!), but the consensus seems to be that there's still quite a bit of work left to do before LLVM can replace the commercial and open-source compilers (IAR, CCE, CrossWorks, mspgcc, and so on) that

Hello > inline asm code is like below: > > void test(unsigned short a) { >    asm("myinstr          my16bitreg, %0"::"r"(a)); > } > I want it generate instruction "myinstr          my16bitreg, r15" > > I execute > llc test.bc -march = msp430 -o test.s > then it reports > "LLVM ERROR: Couldn't allocate input reg for constraint

Hi Anton, Need i write additial c/c++/td code for my target to support inline asm? Regrads 2009/12/18 Anton Korobeynikov <anton at korobeynikov.info> > Hello > > > inline asm code is like below: > > > > void test(unsigned short a) { > > asm("myinstr my16bitreg, %0"::"r"(a)); > > } > > I want it generate instruction

Who is a code owner for MSP430 target? I know that a lot of work on this target is done by Anton Korobeynikov (aka asl) but he is not listed as a code owner in CODE_OWNERS.TXT. I would like to get my D20162 reviewed, but I don't know who I can add as a reviewer.

Please CC me. I will review. On Mon, May 23, 2016 at 2:46 PM, Vadzim Dambrouski via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Who is a code owner for MSP430 target? I know that a lot of work on this target is done by Anton Korobeynikov (aka asl) but he is not listed as a code owner in CODE_OWNERS.TXT. I would like to get my D20162 reviewed, but I don't know who I can add as a

Thank you. I don't know what CC means, but I will ping the diff so you can get an email. > On May 23, 2016, at 15:06, Anton Korobeynikov <anton at korobeynikov.info> wrote: > > Please CC me. I will review. > > On Mon, May 23, 2016 at 2:46 PM, Vadzim Dambrouski via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Who is a code owner for MSP430 target? I

> On May 23, 2016, at 5:06 AM, Anton Korobeynikov via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Please CC me. I will review. Anton, should you be the formal code owner? -Chris

>> Please CC me. I will review. > Anton, should you be the formal code owner? For now I think - yes. At least as someone to review patches as a last resort :) -- With best regards, Anton Korobeynikov Department of Statistical Modelling, Saint Petersburg State University

Hi everyone, inline asm code is like below: void test(unsigned short a) { asm("myinstr my16bitreg, %0"::"r"(a)); } I want it generate instruction "myinstr my16bitreg, r15" I execute llc test.bc -march = msp430 -o test.s then it reports "LLVM ERROR: Couldn't allocate input reg for constraint 'r' !" What's the reason?

On Fri, Jun 11, 2010 at 2:55 PM, Ben Ransford <ransford at cs.umass.edu> wrote: > Yesterday I noticed that MSP430 argument passing is broken in trunk; > see http://llvm.org/PR6573 for details and testcases.  The problem is > that calls aren't being preceded by instructions that put the > arguments into registers.  I backtracked my working copy and then > stepped forward

On Thu, Jul 6, 2017 at 1:35 AM, Nicholas Wilson < iamthewilsonator at hotmail.com> wrote: > Luís, try using the -no-integrated-as flag to execute the assembler for > you. > We should probably make that the default for MSP430. > Cool. When I did that on macOS, LDC generated a lot of complaints, possibly because it is assuming mach-o files. I tried changing from -mtriple=msp430