similar to: About a new porting of GlobalIsel for RISCV

This question came about through reviewing work from Leslie Zhai on GlobalISel support for RISC-V, which also motivated me to revisit code which I've always felt was a bit clunky. Calling convention lowering in LLVM is typically handled by functions conforming to the CCAssignFn typedef: typedef bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT,

On 4 January 2018 at 17:10, Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> On 3 Jan 2018, at 14:00, Alex Bradbury via llvm-dev <llvm-dev at lists.llvm.org> wrote: > I haven't dug into the GlobalISel calling convention code much but I can comment on the MipsCCState. Thanks for the insight Daniel, much appreciated. >> * MipsCCState: adds bool

Hi LLVM developers, Don't be quiet :) we need your suggestions for supporting custom CCState, CCAssignFn in D41700. And also RegisterBank in D41653. because it needs to consider about how to support variable-sized register classes concept implemented in D24631. And I think you might have same question when porting to GlobalISel for your Targets, so please give us some directions, thanks

> On 4 Jan 2018, at 10:51, Alex Bradbury <asb at lowrisc.org> wrote: > > On 4 January 2018 at 17:10, Daniel Sanders via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >>> On 3 Jan 2018, at 14:00, Alex Bradbury via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> I haven't dug into the GlobalISel calling convention code much but I can comment on the

I haven't dug into the GlobalISel calling convention code much but I can comment on the MipsCCState. > On 3 Jan 2018, at 14:00, Alex Bradbury via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > This question came about through reviewing work from Leslie Zhai on GlobalISel > support for RISC-V, which also motivated me to revisit code which I've always > felt was a

Hi! So far, GlobalISel only supports very basic inline assembler constructs (no input/output operands, only simple memory clobbers). In [0], I'm adding support for generic register, immediate, memory and clobber constraints. The code is more or less a direct port from the handling in SelectionDAGBuilder. Before moving on with target specific constraints, I'd like to discuss the

Hi LLVM developers, I am not available from February 11th to February 25th due to Chinese Spring Festival and my sincere thanks goto: Anna Zaks:     She lead me to the LLVM family and reviewed my patch for clang analyzer MallocChecker carefully and patiently. Дуже дякую Artem Dergachev:     He reviewed my patches for clang analyzer some Checkers carefully. Большое спасибо Dylan McKay:

I am finding some weird behavior in the CallGraph, and am not sure what am I doing wrong. When trying to traverse nodes in the CallGraph I get stuck in nodes representing external functions. Take the following code: ----- #include <stdio.h> int main() { printf( "Hello World!\n" ); } ----- If I try to traverse the CallGraph using the following code: ----- CallGraph CG

As part of our OpenVMS-specific changes, we're adding an arg-count to all of our calls. We've done this as part of callLowering to put the # of slots used into %ah and leaving %al to hold the standard info about vector registers.  That part is working. However, we're struggling somewhat on the code in the prologue to capture the %ah value to then be obtained by our

I find the lldb cannot display structure type information, such as "print ArgLocs.size()" as follows, -> 593 CCValAssign &VA = ArgLocs[i]; 594 EVT ValVT = VA.getValVT(); 595 ISD::ArgFlagsTy Flags = Ins[i].Flags; 596 bool IsRegLoc = VA.isRegLoc(); (lldb) print ArgLocs.size() error: call to a function

This may be a debug info bug, if you could reduce it down a bit and file a bug that'd be appreciated. Thanks. -eric On Sun, Jan 27, 2013 at 12:11 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I find the lldb cannot display structure type information, such as "print > ArgLocs.size()" as follows, > > -> 593 CCValAssign &VA = ArgLocs[i]; >

Hi, I define a customized node with customized type. The job of this customized node is to move a value from one register class to another class. I find that if there is no use of the destination register, this node will be deleted from SDAG. For some reasons, I want to keep this node. So I attach mayStore attribute to this node and I hope it will not be deleted. However, it does not work like I

Hi, All, I'm trying to build a customized backend and I need to lower the formal arguments like this: There are several specific registers just for storing formal arguments. And also there are several general purpose registers for computation. If there is an instruction which uses parameters, I should first use a move instruction, which moves the value to general purpose register. For

Hi Arnold, Thanks for the patch. Some questions and commons: 1. Have you test it against the llvm test suite? Does it work if fp elimination optimization is turned off? 2. Please follow llvm coding convention and make sure every line fits in 80 columns. 3. enum NameDecorationStyle { None, StdCall, - FastCall + FastCall, + FastCC // the normal fastcc calling convention }; Why is

Hi Evan, first off thanks to you and Chris for taking time. On 6 Sep 2007, at 00:57, Evan Cheng wrote: > We'd like to see tail call optimization to be similar to the target > independent lowering of ISD::CALL nodes. These are auto-generated > from ???CallingConv.td files. Some target specific details such as > function address register (ECX in your example) should be coded in

Begin forwarded message: > From: Evan Cheng <evan.cheng at apple.com> > Date: 11 September 2007 19:26:39 GMT+02:00 > To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > Subject: Re: [LLVMdev] RFC: Tail call optimization X86 > Reply-To: LLVM Developers Mailing List <llvmdev at cs.uiuc.edu> > > Hi Arnold, > > Thanks for the patch. Some questions