Displaying 20 results from an estimated 3000 matches similar to: "[FPEnv] Rust/Go/Swift/Flang/other llvm IRBuilder needs?"
2016 Mar 16
2
IRBuilder Assignment ( '=' ) operator?
In my code assembly system I have the various LH-RH operators, ADD, ADDF, SUB, etc, using CreateAdd, CreateFAdd, etc, however I cant seem to locate the correct function/s for the assignment operator.
What's the correct function/s in the IRBuilder for assigning a value?
- Paul
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2016 Mar 16
3
IRBuilder Assignment ( '=' ) operator?
However I need the standard assignment operator so I can assign the value of a temporary to that of another temporary, or to create a new temporary from an existing one.
- Paul
________________________________________
From: Tim Northover <t.p.northover at gmail.com>
Sent: 16 March 2016 13:11
To: Paul Hancock
Cc: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] IRBuilder Assignment (
2019 May 29
2
[RFC] Add support for options -fp-model= and -fp-speculation= : specify floating point behavior
Intel would like to contribute a patch to implement support for these Intel- and Microsoft -fp options. This message is to describe the options and request feedback from the community.
-fp-model=[precise|strict|fast|except[-]] and
-fp-speculation=[fast|strict|safe]
This contribution would dovetail with the llvm patch "Teach the IRBuilder about constrained fadd and friends" which is
2018 Oct 02
3
[FPEnv] FNEG instruction
On Tue, Oct 2, 2018 at 12:09 PM Kevin Neal <Kevin.Neal at sas.com> wrote:
> If we don’t have constrained intrinsics for some of the fp math
> instructions then aren’t we risking non-strict optimizations?
>
So far we've only added constrained FP intrinsics for operations that have
side effects (i.e. can trap).
The quiet-computational sign-bit operations are special. They never
2018 Sep 26
2
[FPEnv] FNEG instruction
Well, yes, they are different operations. And, yes, this needs to be corrected. This wasn’t my point. It’s a given.
I was getting at the _declared_ absence of side effects and what promises we make to anyone using the new fneg instruction. Is this a promise we want to make?
From: Cameron McInally <cameron.mcinally at nyu.edu>
Sent: Wednesday, September 26, 2018 2:30 PM
To: Kevin Neal
2016 Mar 16
3
IRBuilder Assignment ( '=' ) operator?
I partially worked out that to do an assign I will need to manually assign a temporary first and then load data into it, which also means I'll need to set up a temporaries list in my code assembler as allocations must be done before anything else? or is it fine to allocate a variable mid-way through a function and the compiler will manage it?
With that as well, if I had a function that loads
2018 Sep 26
2
[FPEnv] FNEG instruction
Do we really want to have fneg be the only instruction with guaranteed no side effects? That just sounds like a gotcha waiting to happen. Or it could result in horrible code depending on the architecture.
I’m still leaning towards having both an intrinsic and an instruction, and if they happen to have the same behavior then that’s fine. If fneg is to be a special instruction with extra promises
2018 Sep 26
2
[FPEnv] FNEG instruction
I have no example side effects in hand. But LLVM targets a bunch of architectures, and who knows what the future holds. So it may be prudent to not promise too much so as to leave ourselves an escape hatch.
Doesn’t LLVM target some chips that have floating point instruction sets that are not IEEE compliant? Can we be certain that no new LLVM target will ever have to jump through hoops to avoid
2018 Aug 30
2
[FPEnv] FNEG instruction
On Thu, Aug 30, 2018 at 11:14 AM, Tim Northover <t.p.northover at gmail.com>
wrote:
> ...
> I don't think it matters for the question at hand, but I tested
> AArch64 too and it exhibits the behaviour you were describing. That
> is, we'd have problems if an fsub -0.0 was actually CodeGened like
> that (it's not, of course).
Great data point. So it's not just
2018 Sep 11
2
[FPEnv] FNEG instruction
+1 for an explicit FNEG instruction, since as previously discussed, it has
stricter requirements for what value may be returned by the operation. And
strengthening the requirement on FSUB is not feasible when the values are
variables rather than literals.
That is:
FSUB(-0.0, NaN) = either NaN *or* -NaN
FSUB(-0.0, -NaN) = either NaN *or* -NaN
FNEG(NaN) = -NaN
FNEG(-NaN) = NaN
On Tue, Sep 11,
2018 Oct 01
6
[FPEnv] FNEG instruction
I don't see any controversy for the preliminary requirement of
removing BinaryOperator::isFNeg()
and friends, so start with that?
That work may reveal other potential regressions that we can patch in
advance too.
Other than that, I think there's really only a question of do we want 1 or
both of fneg and fneg_constrained (and if we choose both, then I assume
we'd also add
2015 Mar 10
4
[LLVMdev] noob IR builder question
I am trying to get a handle on IR builder, at least some basics. I ran through a tutorial here: Create a working compiler with the LLVM framework, Part 1 <http://www.ibm.com/developerworks/library/os-createcompilerllvm1/>, and it worked well enough. I have some simple code that creates a hello world IR. I am trying to now bring in some concepts from the Kaleidoscope tutorial, namely
2015 Apr 17
2
[LLVMdev] how to use "new instruction()"
It seems that the problem was because I used builder.CreateFAdd to create
a <2 x double> vectortype FADD instruction. It works if I use it to create
the scalar version FADD. I want to have an instruction like: *%2 = fadd <2
x double> undef, <2 x double> undef. *The following is the way I used to
create the vectorized FADD instruction:
//pInst is a double type instruction
2015 Apr 17
2
[LLVMdev] how to use "new instruction()"
Thanks Nick, that's something what I am trying to implement as the
following. But it seems I still only get the constant value not the
instruction. Could you please go over the following instruction and see
what wrong with it? Thanks for your time again.
Value *vecVal = NULL;
IRBuilder<> builder(&*pInst);
Type *vecTy = VectorType::get(Type::getDoubleTy(ctxt), 2);
Value
2015 Apr 17
2
[LLVMdev] how to use "new instruction()"
I got it. Thanks, Nick. So, it is back to the previous problem. If I have
the following instruction:
%3 = fadd double %1, double %2
I want to change it into
%6 = fadd <2 x double> %4, double %5
where %4 = <double %1, double %1>, %5 = <double %2, double %2>, how can I
do this?
Thanks,
Best
On Fri, Apr 17, 2015 at 1:56 AM, Nick Lewycky <nicholas at mxc.ca> wrote:
>
2018 Sep 11
2
[FPEnv] FNEG instruction
Which exactly was the plan?
Add a new, regular instruction?
Add a new constrained math intrinsic?
Both?
Andrew Kaylor made a good point here:
* As I said, all LLVM IR FP instructions are //assumed// to have no side effects. I'm not sure we want an instruction that goes beyond this to be //defined// as having no side effects. It adds a complication to the language and introduces
2015 Apr 17
2
[LLVMdev] how to use "new instruction()"
Value * is the instruction.
use dyn_cast<Instruction> to get to it.
On Thu, Apr 16, 2015 at 11:39 PM zhi chen <zchenhn at gmail.com> wrote:
> But IRBuilder.CreateXYZ only returns a "VALUE" type. Can I get the
> instruction created by it? For example,
>
> IRBuilder<> builder(&*pinst);
> Value *val = builder.CreateFAdd(LV, RV, "");
>
2018 Sep 26
3
[FPEnv] FNEG instruction
On Wed, Sep 26, 2018 at 9:32 AM Sanjay Patel <spatel at rotateright.com> wrote:
>
>
> On Tue, Sep 25, 2018 at 7:47 PM Cameron McInally <cameron.mcinally at nyu.edu>
> wrote:
>
>>
>> This is the first time I'm looking at foldShuffledBinop(...), so maybe a
>> naive question, but why not do similar shuffle canonicalizations on unary
>> (or
2020 Jan 08
3
Flang landing in the monorepo - next Monday!
Hal, Eric, Johannes, David and Peter,
I lead the development of OpenMP for AMD GPUs and work with others at AMD
who support OpenMP on AMD CPUs. On behalf of our development teams, we
greatly appreciate your efforts to move the development of flang into a
subproject in the llvm-project repository and to integrate this development
effort into the overall LLVM development community.
Like most
2018 Sep 25
2
[FPEnv] FNEG instruction
On Tue, Sep 25, 2018 at 1:39 PM Sanjay Patel <spatel at rotateright.com> wrote:
> I have 1 concern about adding an explicit fneg op to IR:
>
> Currently, fneg qualifies as a binop in IR (since there's no other way to
> represent it), and we have IR transforms that are based on matching that
> pattern (m_BinOp). With a proper unary fneg instruction, those transforms
>