similar to: empty list assertion

sorry, ignore my earlier email. I followed this: https://stackoverflow.com/questions/42881901/how-to-compile-some-modules-in-llvm-with-debug-mode-others-with-release-mode and got the debug build completed. On Sat, Jan 5, 2019 at 10:02 AM Peter Teoh <htmldeveloper at gmail.com> wrote: > will this help? > > >

In the definition of register classes, have you provided any value types for each class? -Krzysztof On 1/9/2019 7:19 PM, m m via llvm-dev wrote: > The file that is causing this assertion contains only 3 include statements > > |//===-- ABCOther.td - Describe the ABC Target Machine ----*- tablegen > -*-===// // // >

Hello, i want to work with these types v32f32, v32f64.... in llvm which are undefined in the backend? But v32i32, v32i64 are already defined so i am able to use these. but for other types such as v32f32, v32f64 although i have defined them appropriately in all the files like machinevaluetype.h, valuetypes.cpp etc. i have checked it many times but still getting the following error when build in

Thank you so much. it run fine. Can you please resolve following issue; I now have support for v2048i32 but my backend supports v64i32 so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the only difference between 2 is if its orginally v2048i32 i want my registers assignment from REG_A set. if its v64i32 originally, then i want registers from set REG_B. How to accomplish

I would be very grateful if you specify whether there is some way to allocate registers (different order) / from different register sets to the same instruction based on the vector width/ no of iterations. I have tried several alternatives but could not succeed. Also I have asked this question many times but no one responds. Is there something wrong with this?? Kindly guide me. Thank You On

Are multi-output patterns in TableGen supposed to work, or is that a known limitation in the current implementation? If I have TableGen code like the following... 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>; 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>; 1244 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0,

Thanks for the info. Is this on someone's list of things to do? On Sun, Jan 6, 2013 at 7:41 PM, Bob Wilson <bob.wilson at apple.com> wrote: > > On Jan 4, 2013, at 9:52 AM, Justin Holewinski <justin.holewinski at gmail.com> > wrote: > > Are multi-output patterns in TableGen supposed to work, or is that a known > limitation in the current implementation? >

On Jan 4, 2013, at 9:52 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Are multi-output patterns in TableGen supposed to work, or is that a known limitation in the current implementation? It is a known limitation. You have to write C++ code to match patterns with multiple outputs. > > If I have TableGen code like the following... > > 1242 def SDTTestNode

It has been something we've talked about for years, but I'm not aware of anyone working on it right now. On Jan 6, 2013, at 5:34 PM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Thanks for the info. Is this on someone's list of things to do? > > > On Sun, Jan 6, 2013 at 7:41 PM, Bob Wilson <bob.wilson at apple.com> wrote: > > On Jan 4,

bio_add_page() requires non-NULL bio ptr for dereferencing. Signed-off-by: Peter Teoh <htmldeveloper@gmail.com> --- extent_io.c.orig1 2008-03-16 12:43:59.000000000 +0800 +++ extent_io.c 2008-03-16 12:45:03.000000000 +0800 @@ -1729,6 +1729,7 @@ static int submit_extent_page(int rw, st if (bio_ret && *bio_ret) { bio = *bio_ret; + BUG_ON(!bio);

Hi My goal is that given a binary and the corresponding input. I want to know what IR level basic blocks are covered. I need the detail information, which is the set of all the covered BBs rather than just a number. I want to know whether there are some tools that can support this requirements. If not, I think maybe instrumentation can helps. However, I do not know too much about this. Any

I was playing around with btrfs, and did a mkfs.btrfs on one of my partition. Mistakes, it was my data partition (ext3 based). I have not yet mounted the device, but the mkfs.btrfs continued to completion. Is it possible to salvage my ext3 filesystem? Anyway to reverse the effect of mkfs.btrfs? Thank you for your help/answer. -- Regards, Peter Teoh

First the following errors are logged in dmesg: [ 31.891848] mtrr: base(0xc0000000) is not aligned on a size(0xff00000) boundary [ 32.343580] Xorg:3090 conflicting memory types c0000000-cff00000 uncached<->uncached-minus [ 32.343585] reserve_memtype failed 0xc0000000-0xcff00000, track uncached, req write-back [ 32.344431] Xorg:3090 conflicting memory types fd000000-fe000000

I searched the archives and found this from last month: I ran into the same problem and fixed it by forcing the MVT::SimpleValueType enum to be 64 bits so that all of the types in the union later in the class are the same size. I tested this on ppc64 and x86_64. Index: include/llvm/CodeGen/ValueTypes.h =================================================================== ---

Hi, I am beginning the porting process for Linux on System z (aka IBM Mainframe). I thought I¹d build LLVM first with the c and cpp backends so that tools like TableGen would be created that I¹d then use to process the .td files that I¹ll be creating. So I used svn to grab the code from the repository and ran configure and make. However, the build breaks at this point: llvm[1]: Building

Hi, > llvm[1]: Building Intrinsics.gen.tmp from Intrinsics.td > tblgen: IntrinsicEmitter.cpp:163: void EmitTypeForValueType(std::ostream&, > llvm::MVT::SimpleValueType): Assertion `false && "Unsupported ValueType!"' > failed. this came up before IIRC, but I don't remember the details - buggy system compiler? Try searching the archives. Also, if you

Hi Eli, Thanks for your response. Please see my responses below. On 10/12/2011 00:28, Eli Friedman wrote: > On Fri, Dec 9, 2011 at 4:46 AM, Llopard Ivan<ivanllopard at gmail.com> wrote: >> Hi all, >> >> I am writing a back-end for a processor that has complex type registers. >> It has two functional units to perform complex multiplications. >> From clang,

How do we probe the Xen hypervisor, while running as the dom0 (which is the GUI frontend for us, and running as guest)? Since the entry to hypervisor is controlled, I supposed it will need a patch before systemtap can be used to probe the Xen hypervisor, right? Or is it not a logical thing to do? My target of interest will be to trace/analyze the behavior of the Xen hypervisor, and the

Hi All, I am trying to read group descriptor from disk. I am able to read the superblock structure successfully. But I am not getting successful to get the group descriptor. Here is my code. Please check out what is missing. #include<linux/ext3_fs.h> #include<sys/types.h> #include<sys/stat.h> #include<stdio.h> #include<unistd.h> #include<fcntl.h>

Hi all, I am writing a back-end for a processor that has complex type registers. It has two functional units to perform complex multiplications. From clang, I emulate a complex multiplication using vectors and, at the IR, I got this tblgen-friendly pattern (real component) : (set RARegs:$dst, (insertelt RARegs:$src, (i16 (trunc (add (ncmul (sext (i16