similar to: Coupling between CaptureTracking and its users

Is there any particular reason that CaptureTracking.h isn't folded into ValueTracking.h? I was looking for the method to check whether a pointer would be captured and looked in ValueTracking.h, unaware that a new header had been created for that one method. Would anyone mind if I folded CaptureTracking into ValueTracking? Nick -------------- next part -------------- An HTML attachment was

I have a problem for specific mailbox. In mail.err file I see a lot: Nov 2 07:41:17 s1 dovecot: imap(artur at example.pl): Error: unlink(/var/vmail/example.pl/artur/Maildir/dovecot.index.cache) failed: No such file or directory (in mail-cache.c:28) Nov 2 07:41:17 s1 dovecot: imap(artur at example.pl): Error: Corrupted index cache file /var/vmail/example.pl/artur/Maildir/dovecot.index.cache:

Ok, I will try to do this but should I do some backup of INBOX earlier? 2018-11-02 20:21 GMT+01:00 Sami Ketola <sami.ketola at dovecot.fi>: > > > On 2 Nov 2018, at 20.58, Poliman - Serwis <serwis at poliman.pl> wrote: > > I have a problem for specific mailbox. In mail.err file I see a lot: > > Nov 2 07:41:17 s1 dovecot: imap(artur at example.pl): Error:

I have strange problem. In last Friday I had a problem with dovecot. It didn't see directories with mailboxes in /var/vmail. Somehow it crashed because probably two things (a lot of this type of lines in mail.err file): *Nov 23 07:05:02 s1 dovecot: lda(poli at poli.li <poli at poli.li>): Error: User initialization failed: Initializing mail storage from mail_location setting failed:

If there are any students looking for ideas, here a couple of projects you might consider. p.s. Anyone know where in the repo the OpenProjects page is? I'd expected it to be the docs/ folder of the LLVM repo, but it wasn't. Transactional Memory Optimization Intel recently introduced transactional memory support in hardware. This project would consist of implementing optimizations

Hi Peter, Thanks for the reply. I agree that the base class vtable may be not referenced by a derived class. However, the vtable of a derived class has to reference its parent type_info, and so having type_info internalized means that the class is final, doesn’t it? Thanks, Nikolai From: Peter Collingbourne [mailto:peter at pcc.me.uk] Sent: Wednesday, December 6, 2017 4:36 AM To: Gainullin,

Hi! I have a question about whole program devirtualization pass. According to my understanding devirtualization is performed only for the classes that have hidden LTO visibility and this visibility is controlled by attributes in the source level or command line options. So visibility analysis is currently performed only in the front-end. But LLVM has LTO internalization pass that uses

Hi Sanjay, Some time ago you implemented a sext(add_nsw(x, C)) --> add(sext(x), C_sext) transformation in X86ISelLowering https://reviews.llvm.org/D13757 Is there any reason why this transformation is limited to sexts and doesn’t support zexts? Thanks, Artur -------------- next part -------------- An HTML attachment was scrubbed... URL:

https://bugzilla.mindrot.org/show_bug.cgi?id=2726 Bug ID: 2726 Summary: Uploading of large files (1GB+) fails when using SFTP in chrooted configuration Product: Portable OpenSSH Version: 7.3p1 Hardware: amd64 OS: Linux Status: NEW Severity: normal Priority: P5

PR43308 describes a case where StackProtector fails to protect against a fairly simple smash. This problem started after r363169, which removed StackProtector's own analysis function HasAddressTaken, and used CaptureTracking's PointerMayBeCaptured instead. The problem here is that "pointer is captured" and "pointer could be used to smash the stack" are not equivalent

Hi there lowering experts, Can the llvm.mem* intrinsics ever turn into a library call? Or do they invariably turn into inline code? This comes up because there was a patch to StackProtector to use CaptureTracking instead of a home-grown analysis, which changes the treatment of calls to intrinsics. (The old code treated them as normal calls, the new code decides intrinsics can never capture.)

One of the arguments for doing this earlier is inline cost perception of the original pattern. Reading i32/i64 by bytes look much more expensive than it is and can prevent inlining of interesting function. Inhibiting other optimizations concern can be addressed by careful selection of the pattern we’d like to match. I limit the transformation to the case when all the individual have no uses other

Ok, thanks. Are there any plans to reintroduce it on the IR level? I'm not confident this is strictly necessary, but in some cases not having load widening ends up really bad. Like in the case where vectorizer tries to do something about it: https://godbolt.org/z/60RuEw https://bugs.llvm.org/show_bug.cgi?id=42708 At the current state I'm forced to use memset() to express uint64 load from

pon., 26 lis 2018 o 09:25 Aki Tuomi <aki.tuomi at open-xchange.com> napisa?(a): > > On 26.11.2018 10.01, Poliman - Serwis wrote: > > I have strange problem. In last Friday I had a problem with dovecot. It > didn't see directories with mailboxes in /var/vmail. Somehow it crashed > because probably two things (a lot of this type of lines in mail.err file): > *Nov 23

> On 29 Sep 2016, at 03:23, Sanjoy Das <sanjoy at playingwithpointers.com> wrote: > > Hi Artur, > > Artur Pilipenko via llvm-dev wrote: > > One of the arguments for doing this earlier is inline cost > > perception of the original pattern. Reading i32/i64 by bytes look much > > more expensive than it is and can prevent inlining of interesting > >

If we do load combining at the IR level, one thing we'll need to give some thought to is atomicity.  Combining two atomic loads into a wider (legal) atomic load is not a reversible transformation given our current specification. I've been thinking about a concept I've been tentatively calling "element wise atomicity" which would make this a reversible transform by

Hi all,I'm working on my own backend for a custom CPU. I have defined paired registers for 64bit operations, however to set a 64bit paired register with 64bit immediate I have to set each register in that pair separately with the higher and the lower 32bits of the immediate. Could anyone give me an advice how to describe it in *InstructionInfo.td or point me to something similar in the LLVM

Hi, Can I ask what is the status of load widening. It seems there is no load widening on IR at all. // Paweł On Wed, Oct 5, 2016 at 1:49 PM Artur Pilipenko via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Philip and I talked about this is person. Given the fact that load > widening in presence of atomics is irreversible transformation we agreed > that we don't want to do

Yes, I'm running all the existing passes that I know how to run. I didn't know they returned change-made. Thanks! On Mon, Dec 21, 2015 at 12:36 PM, Artur Pilipenko < apilipenko at azulsystems.com> wrote: > Are you going to run some of the existing passes? Why can’t you just use > the returned change-made value from the passes? > > Artur > > > On 20 Dec 2015, at

Hi Philip, > On Mar 22, 2016, at 4:43 PM, Philip Reames via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > If there are any students looking for ideas, here a couple of projects you might consider. > > p.s. Anyone know where in the repo the OpenProjects page is? I'd expected it to be the docs/ folder of the LLVM repo, but it wasn't. Is it what you're