similar to: Liveness Analysis

So what is the status about LiveVariables. Is there a plan to remove it? After searching in old lvm-dev-mails it is mentioned that LiveVariable still exists due to one pass needing it. And a comment in TargetPassConfig.cpp indicates that the pass in question is TwoAddressInstruction: // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

On Feb 8, 2013, at 4:37 PM, Cameron Zwarich <zwarich at apple.com> wrote: > On Feb 8, 2013, at 4:20 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> On Feb 8, 2013, at 4:03 PM, Cameron Zwarich <zwarich at apple.com> wrote: >> >>> How much of the work is done here? I'd be happy to do the phi elimination part, since I basically did that

Hi, I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from

Hi, I have cases of instruction pairs, where one is cheaper 2-address, and the other 3-address. I would like to select the 2-addr instruction during isel, but use the 3-addr instruction to avoid a copy if possible. I find that TwoAddressInstructionPass::isProfitableToConv3Addr() is only checking for the case of a physreg copy, and so leaves the majority of cases as they are (2-address). I

> > Hello, llvmers. Could someone explain me a little about the opt tool? I am > > having problems to load a MachineFunctionPass using opt. I have this pass: > > MachineFunctionPass's cannot be used as part of opt, they can only be used > as part of LLC. Further, you have to explicitly modify the target you are > interested in to add it to the pass manager for that

Hello to all LLVM Developers. The LLVM IR is in strict SSA form (i.e. every variable is defined before it is used along every path from the entry to exit point)? According to the documentation, currently the LLVM IR is in the SSA form, but I don't see additional information about *strict* SSA form. The strict SSA form provide opportunities of optimization in register allocation, because is

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A similar setting occurs with ARM Thumb code which for many instructions has a short 2-address encoding and a longer 3 address form. As far as I know this is done by selecting the 3 address form and rewriting them to 2-address after register allocation where possible. See lib/Target/ARM/Thumb2SizeReduction.cpp. - Matthias > On Sep 29, 2015, at 2:22 PM, Quentin Colombet via llvm-dev

On Feb 8, 2013, at 4:45 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > On Feb 8, 2013, at 4:37 PM, Cameron Zwarich <zwarich at apple.com> wrote: > >> I'll try doing that. Did you ever add a way to update LiveIntervals quickly after splitting an edge or will that have to finally be added? I can skip the critical edge splitting for now. > > That

I'm debugging a problem with a custom pass and I was surprised to discover that LiveIntervalAnalysis depends on PHIElimination. Why is that so? Intervals could be useful for all sorts of things beyond register allocation. Just curious. Is there something about the design of LiveIntervals that it needs the out-of-SSA conversion? -Dave

At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level

On Mon, 1 May 2006, Fernando Magno Quintao Pereira wrote: > Hello, llvmers. Could someone explain me a little about the opt tool? I am > having problems to load a MachineFunctionPass using opt. I have this pass: MachineFunctionPass's cannot be used as part of opt, they can only be used as part of LLC. Further, you have to explicitly modify the target you are interested in to add it

On Jan 3, 2014, at 1:06 PM, Andrew Trick <atrick at apple.com> wrote: > > On Jan 3, 2014, at 12:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > >> >> On Jan 3, 2014, at 11:01 AM, Andrew Trick <atrick at apple.com> wrote: >> >>> >>> On Jan 3, 2014, at 4:58 AM, Haishan <hndxvon at 163.com> wrote: >>>

Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend

Hello, all, I want to implement the register allocation algorithm described in the paper "Register Allocation via Coloring of Chordal Graphs, APLAS'05" in LLVM. This is a graph coloring algorithm that can find an optimal coloring of the interference graph in most of the cases. I've downloaded LLVM last week, and started studying the code. Basically, I have to implement: 1) A

Hello, llvmers. Could someone explain me a little about the opt tool? I am having problems to load a MachineFunctionPass using opt. I have this pass: #include "llvm/Pass.h" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include <iostream> using namespace llvm; namespace { struct MacFoo : public MachineFunctionPass { virtual

Hi, Is there a way to print the register liveness information into the assembly file or as some intermediate listing? To be more precise, I am looking at figuring out the following information in an assembly file/listing. Say, for simplicity, our register set is only { rsp, rbp, eax } subq $16, %rsp // rsp is killed here, eax and rbp are live movl $0, -4(%rbp) // rbp is killed here,

Hello all Currently I want to use the accurate liveness information when writing a *target independent* FunctionPass based on LLVM. The one I can find is LiveValues, a FunctionPass. But it doesn't use classic dataflow equation and can only provide approximate and conservative result. The another one is LiveVariables which use classic data flow equation, but it comes from Clang's analysis

Note that this only works for targets that say TargetRegisterInfo::trackLivenessAfterRegAlloc()== true. > On Feb 16, 2017, at 1:21 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Anitha, > > The liveness information is usually dropped after regalloc. > Therefore the short answer is no, this information is not available before producing