similar to: How to add a barrier pseudo instruction?

Hi Tim, Thank you a lot for your reply. So IIUC, optimization passes in opt do not reorder IR instructions, only passes in llc that move MIR instructions around. Is it correct? On the back-end (llc) side, hasSideEffects might prevent some reordering. But I just learn about TargetInstrInfo::isSchedulingBoundary. Can you tell me what are the differences between the two please? Thank you very much

On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > We improved our instruction itineraries and now we're seeing our > testcases for fence instructions break. > > > > For example, we have this testcase: > >

We improved our instruction itineraries and now we're seeing our testcases for fence instructions break. For example, we have this testcase: @write_me = external global i32 @read_me = external global i32 ; Function Attrs: nounwind define i32 @xstg_intrinsic(i32 %foo) #0 { entry: ; CHECK: store r0, r1, 0, 32 ; CHECK-NEXT: fence 2 %foo.addr = alloca i32, align 4 store i32 %foo,

Mhm I see now, thanks for your explanation! Son Tuan Vu On Fri, Mar 16, 2018 at 10:58 PM, Vedant Kumar <vsk at apple.com> wrote: > > On Mar 16, 2018, at 2:30 PM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > Hi Vedant, > > Thank you for your reply. I think I can make this debugify-each mode, but > I guess this is reserved for your GSoC project ? > >

Hi Vedant, Thanks for your reply. More comments inline. Son Tuan Vu On Fri, Apr 20, 2018 at 10:19 PM, Vedant Kumar <vsk at apple.com> wrote: > Hi, > > + Chandler, who has a lot more experience with our pass managers. > > On Apr 20, 2018, at 12:56 PM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > + Vedant: what do you think about the last point, since

> On Mar 16, 2018, at 2:30 PM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > Hi Vedant, > > Thank you for your reply. I think I can make this debugify-each mode, but I guess this is reserved for your GSoC project ? No, there's no reserved work. If you'd like to work on this I encourage you to do so. There's plenty of other work slated for the GSoC project.

Hello, Has anyone taken a look at this bug? I really want to fix this, but as Paul pointed out, this requires a lot of care... Thank you for your help Son Tuan Vu On Fri, Apr 27, 2018 at 7:29 PM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > Thank you all for taking a look at this. I pasted the C source then > deleted it because I was afraid that it was too long to read...

Hello all, I came across the code of Verifier, and see that it doesn't modify the IR at all. Why it is not considered as an analysis pass? Actually, this will have impact on debugify-each and print-before/after-all: we are not supposed to print/debugify Verifier pass, but since Verifier is declared as a transformation (well, a non-analysis) pass, we actually do print/debugify it. Thanks for

Hi Vedant, Thank you for your reply. I think I can make this debugify-each mode, but I guess this is reserved for your GSoC project ? However, if I understand correctly, we do not want to take the output of the first check-debugify (I mean the .ll file with potentially all the WARNINGs and ERRORs after the first pass) as input for the second debugify. What we need is to take the fresh output of

Ok, now I think I've found a bug: Consider this C code: void bar(int b) { int a[10]; memset(a, b, 10); } which generates this IR code: define dso_local void @bar(i32 %b) #0 { entry: %b.addr = alloca i32, align 4 %a = alloca [10 x i32], align 16 store i32 %b, i32* %b.addr, align 4 %arraydecay = getelementptr inbounds [10 x i32], [10 x i32]* %a, i64 0, i64 0 %0 = bitcast i32*

+ Vedant: what do you think about the last point, since Debugify is also related? Son Tuan Vu On Thu, Apr 19, 2018 at 6:14 PM, Philip Pfaffe <philip.pfaffe at gmail.com> wrote: > Hi Son, > > PassManagerBuilder is used to populate legacy PassManagers. That role is > taken over by PassBuilder for new-PM passes. > > Cheers, > Philip > > 2018-04-18 13:40 GMT+02:00

Hello all, Does anyone know how to define a pure intrinsic in LLVM IR? I have tried almost every intrinsic property from llvm/include/llvm/IR/Intrinsics.td but haven't found anything. Or maybe this is not supported in the IR yet? Thank you for your help, Best, Son Tuan Vu -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello, Does anyone know if it is possible to RAUW the Metadata? I took a look at the source for it and IIUC, it is not possible. What should I do to implement the RAUW for DINode (more precisely DILocation)? Thank you for your help, Son Tuan Vu -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Johannes, Thanks for your reply. I now see more clearly how things work with these properties. However, what would be an object whose address is potentially known by a callee? I suppose the intrinsic arguments and global variable? So IIUC, if not restricted by *only properties, an intrinsic could access to: - only its arguments if IntrArgMemOnly specified, - its arguments and the global

Hi Vedant, I have tried to implement the fix you proposed, but it didn't work as expected. I created a new *Module* Pass Manager (not Function Pass Manager) and override the *add()* method like this: class DebugifyEachPassManager : public legacy::PassManager { public: void add(Pass *P) override { PassManager::add(createDebugifyPass()); PassManager::add(P);

> On Apr 20, 2018, at 1:46 PM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > Hi Vedant, > > Thanks for your reply. More comments inline. > > Son Tuan Vu > > On Fri, Apr 20, 2018 at 10:19 PM, Vedant Kumar <vsk at apple.com <mailto:vsk at apple.com>> wrote: > Hi, > > + Chandler, who has a lot more experience with our pass managers.

Hello, > On Apr 26, 2018, at 6:44 AM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > Hi Vedant, > > I have tried to implement the fix you proposed, but it didn't work as expected. I created a new Module Pass Manager (not Function Pass Manager) and override the add() method like this: > > class DebugifyEachPassManager : public legacy::PassManager { >

Hello, According to include/llvm/IR/Intrinsics.td, InstrReadMem property indicates that the intrinsic only reads from and does not write to memory. Does this mean that it can read anywhere in the memory? Because we already have 'InstrArgMemOnly' for intrinsics which only access memory that its argument(s) point(s) to. If 'InstrReadMem' really means read from anywhere in the

Thanks for your prompt reply. I didn't build the libc at all, I downloaded a pre-built version of the whole toolchain from https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads, so I guess it is an official version provided by ARM and should work? This version targets ARM Cortex-M and Cortex-R family of processors... Son Tuan Vu On Mon, Mar 12, 2018 at 4:15 PM, Tim Northover

Could you file a bug report about this (bugs.llvm.org <http://bugs.llvm.org/>)? If you don't have an account on bugzilla, I'd be happy to file one for you. Please provide exact instructions to reproduce the issue including any compilation flags. thanks, vedant > On May 7, 2018, at 9:16 AM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > Hello, > > Has