similar to: Risc-v Assembly printer function order

Hi Devs, since risc-v has a register $tp which is thread pointer. is it possible to have __builtin_thread_pointer for RISC-V? I am not sure what could be corresponding instructions? ./kamlesh

I am using llvm-project compiling risc-v programs. llvm-project version:dd8a2013dc1804be1b7d9cffacad2e984300bd22 Instructons to build LLVM+clang: ``` cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/home/llvm/workspace/llvm/llvm-project/llvm_install -DCMAKE_BUILD_TYPE="Release" -DDEFAULT_SYSROOT="/home/llvm/workspace/riscv/riscv-tc-20200220/bin/riscv32-unknown-elf"

For background on these calls, see <http://lists.llvm.org/pipermail/llvm-dev/2019-September/135087.html>. Reminder: the purpose is to co-ordinate between active contributors. If you have support questions etc then it's best to post to llvm-dev. We have a call every alternate Thursday at 4pm GMT, via <https://meet.google.com/ske-zcog-spp>. We have a shared calendar which may help

On 18 August 2016 at 00:08, Renato Golin <renato.golin at linaro.org> wrote: > On 17 August 2016 at 10:14, Alex Bradbury via llvm-dev >> * Codegen >> * Compressed instruction set support (RVC) >> * Benchmarking and comparison to GCC RISC-V (and potentially other archs) > > What about buildbots? > > I'm assuming "check-all" would be enough for

On Tue, 21 Jan 2020 at 01:14, Chris Lattner <clattner at nondot.org> wrote: > > On Jan 16, 2020, at 10:01 AM, Alex Bradbury via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I believe code should be committed to LLVM when it is of sufficient > > quality, when it can be shown to benefit the LLVM user or developer > > communities, and when there is someone

Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V

As you will have seen from previous postings, I've been working on upstream LLVM support for the RISC-V instruction set architecture. The initial RFC <http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> provides a good overview of my approach. Thanks to funding from a third party, I've recently been able to return to this effort as my main focus. Now feels like a good

I built llvm + clang from source, a github clone from today: clang version 11.0.0 (https://github.com/llvm/llvm-project.git 91aa67bf290bc7f877b1b90128284863bc31aa43) I compiled a small program: #include <stdint.h> int main() { uint8_t a = 2; uint8_t b = 5; uint8_t c = a * b; } $ clang -c -target riscv32 -march=rv32imc -g main.c Works fine. The dumped assembly seems to not know

On Wed, 22 Jan 2020 at 19:55, Chris Lattner via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Jan 21, 2020, at 5:00 AM, Alex Bradbury <asb at lowrisc.org> wrote: > >> This all makes sense to me. > > > > That's correct, thanks for the feedback. > > > > I do like the idea from James of having the compiler always spit out a > > note

# Overview and background RISC-V is a free and open instruction set architecture. It is a modular specification, with a range of standard extensions (e.g. floating point, atomics, etc). New standard extensions are developed through RISC-V Foundation working groups. The specifications for such extensions (e.g. vector and bit manipulation) are publicly available, but are still in flux and won't

Is there a full LLVM toolchain that can produce an object file runnable by spike (the risc-v ISA simulator)? I found some toolchains but from what I can tell, they still require that you invoke gcc to the assembly and linkage. Is there a reason llvm-as and lld haven't been ported or is it just because nobody has done it yet? -- Ahmed Samara PhD Student Computer Engineering --------------

Hi all, I am proposing the integration of a backend targeting the RISC-V ISA. RISC-V is a free and open instruction set architecture that was originally developed at UC Berkeley. Future development of the ISA specification will be handled by the 501(c)(6) non-profit RISC-V Foundation and its members <https://riscv.org/membership/?action=viewlistings>. You can find much more information at

--- src/filearch.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/src/filearch.c b/src/filearch.c index 5985b73..cbc8372 100644 --- a/src/filearch.c +++ b/src/filearch.c @@ -56,14 +56,16 @@ cleanup_magic_t_free (void *ptr) # endif COMPILE_REGEXP (re_file_elf, - "ELF.*(MSB|LSB).*(?:executable|shared object|relocatable),

Hi, Sam. I think that it's a fair comparison. Keep in mind that the GP is only used to reach global variables of local scope and the GOT, where the address of global variables of global scope reside. This model assumes that the distance between the GP and the global data area, GOT and local scope variables is defined at link time. __ Evandro Menezes ◊ SiFive ◊ Austin, TX > On Mar

Michael, Apologies for taking so long to get back to you. Trunk LLVM does not contain support for code generating the V extension yet. The experimental-v support you see there is only MC-layer support, where you can use the V instructions in assembly (including inline assembly). There is currently (today) no way of turning LLVM IR vector intrinsics into RISC-V V extension instructions. Hanna

(please do cc me to preserve thread as i am subscribed digest) Hi folks, i have a requirement to develop a libre licensed low power embedded 3D GPU and VPU and using RISCV as the basis (GPGPU style) seems eminently sensible, and anyone is invited to participate. A gsoc2017 student named Jake has already developed a Vulkan3D software renderer and shader, and (parallelised) llvm is a critical

For background on these calls, see <http://lists.llvm.org/pipermail/llvm-dev/2019-September/135087.html>. Reminder: the purpose is to co-ordinate between active contributors. If you have support questions etc then it's best to post to llvm-dev. We have a call each Thursday at 4pm GMT, via <https://meet.google.com/ske-zcog-spp>. I've created a shared calendar which may help

On Wednesday, 14 September 2016 15:50:20 CEST Richard W.M. Jones wrote: > --- LGTM, just one question below. > + else if (strstr (elf_arch, "UCB RISC-V")) { > + ret = safe_asprintf (g, "riscv%s", bits); > + goto no_strdup; > + } Is this bit of output from `file` reliable at this point, or can it change in the future? I recall the RISC-V is a

On Wednesday, 14 September 2016 15:50:20 CEST Richard W.M. Jones wrote: > --- Ah, I forgot one thing: > + else if (strstr (elf_arch, "UCB RISC-V")) { > + ret = safe_asprintf (g, "riscv%s", bits); > + goto no_strdup; > + } I guess the "riscv16", "riscv32", and "riscv64" should be documented for the

Hi all, At the Barcelona Supercomputing Center, we have been working on an end-to-end vectorizer using scalable vectors for RISC-V Vector extension in context of the EPI Project <https://www.european-processor-initiative.eu/accelerator/>. We earlier shared a demo of our prototype implementation  (https://repo.hca.bsc.es/epic/z/9eYRIF, see below) with the folks involved with LLVM