similar to: Question about target instruction optimization

Yes, such optimizations are something for the "last 20%" of the project, nice to have's. As of now, I have yet to get a feeling of what LLVM can do on its own, depending on what it's from the instruction tables and where it needs help, and how much in other processing stages. As this affects the way how the instruction info table will be set-up, I appreciate your suggestions

For a Z80 backend, "eliminateCallFramePseudoInstr()" shall adjust the stack pointer in three possible ways, e.g. after a function call, depending on the amount (= adjustment size) *and some other rules*: 1. via one or more target "pop <reg>" instructions (SP increments +2 per instruction), using an unused reg (disregarding the contents after the operation), followed

Thanks Bruce, and elaborately as ever. Again, I'm surprised about your very thorough Z80 knowledge when you said you only did little on the ZX81 in the eighties :D OK, understood. I was first thinking about doing something like this for small frames: 1. push bc # 1 byte; 11 cycles - part of call frame-cleanup: save scratch register +-----begin call-related 2. ld

>It should be possible to get llvm to produce very good code for the Z80... Yes, I was thinking that too. These techniques didn't exist back then, so I'm really looking forward to the point where the first regular C sources can be compiled and see the magic happening in action live :) ------------------------------------------------------------------------ *From:* Bruce Hoult

I'm working on a Z80 backend and am trying to efficiently lower SEXT, specifically 8 to 16 bit, in LowerOperation() according to the following rules: The Z80 has 8 bit registers and 16 bit registers, which are aliased versions of two 8 bit registers. 8 bit registers are named A, H, L, D, E and some more. 16 bit registers are HL (composed of H + L), DE (D + E) - and some more - with L and

Hi All, I'm a little stumped by the following problem. I've got a dataset with the following structure: idxy ix iy country (other variables) 1 1 1 c1 x1 2 1 2 c1 x2 3 1 3 c1 x3 . . . . . 3739 55 67 c7 x3739 3740 55 68 c7 x3740 where ix and

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&

I'm working on defining the instructions and implementing the lowering code for a Z80 backend. For now, the backend supports only the native CPU-supported datatypes, which are 8 and 16 bits wide (i.e. no 32 bit long, float, ... yet). So far, a lot of the simple stuff like immediate loads and return values is very straightforward, but now I got stuck with ISD::TRUNCATE, as in:

Hey all Im having a problem... Ok, this is the situation... I have a small product image, on which ive floated a div over it, and defined it as draggable. Now, this works, and i can drag it around no problem. great. but then, what i want to do is, based on the location of that dragable element from the top and the left, to move (using the Effect.MoveBy method) a larger image - so effective

Dear all; Does anyone know how to add grid lines to a persp plot? I've tried using lines(trans3d..) but the lines of course are superimposed into the actual 3d surface and what I need is something like the plot shown in the following link: http://thermal.gg.utah.edu/tutorials/matlab/matlab_tutorial.html I'll appreciate any ideas Thanks PM

Dear List: I am having to build a block-diagonal matrix (vl) and am currently using the following code. I<-diag(sample.size) vl<-kronecker(I,vl.mat) This code works fine, but for large N, it is a huge memory hog. Is there a more efficient method for constructing vl? Thanks, Harold [[alternative HTML version deleted]]

The ivdep pragma is designed to do exactly what the name states - ignore vector dependencies.  Cray Research first implemented this in 1978 in their CFT compiler, and has supported it since. This pragma is typically used by application developers who want vectorized code when the compiler cannot automatically determine safety; it is not equivalent to the OpenMP SIMD pragma in that the compiler is

On Oct 7, 2014, at 2:26 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Dmitry, > > On 7 October 2014 10:50, Dmitry Borisenkov <d.borisenkov at samsung.com> wrote: >> fpfail.s:26: Error: invalid instruction suffix for `ret' >> >> I downloaded Intel manual and haven’t found any mention of retl instruction, > > "retl" is the

I have a question about antialiasing when R generates bitmaps. (This follows a thread on the ggplot2 mailing list.) I mostly use R on Linux, although I sometimes use it in Mac and Windows as well. On Linux, I've found that plotting shapes 15-18 via cairo results in bad-looking output. The points are not antialiased, and they are jagged and misshapen. Plots generated in Windows also aren't

I've found the need to compute a version of order(x,y) where I want the sort order for *increasing* x and *decresing* y ... something we could imagine could be provided in the future as order(x,y, decreasing = c(FALSE, TRUE)) i.e., using a 'vectorized' decreasing argument. {No, I'm not volunteering right now!} I've found the following R-level solution and like to quiz

I've mentioned my sneaky plans to target the MOS6502 here before. The big issue I think is that a lot of instructions don't really have a choice for output register. It all just goes into the accumulator, X index, or Y index based on the specific instruction. So, my question is, when I'm defining my ins, outs and registers for these instructions, is it going to be a problem that

On Apr 18, 2007, at 2:07 PM, Evan Cheng wrote: > > On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > >> I noticed that the TableGen code emitter generator assumes that >> the instruction fields are declared in the instruction format in >> the same order that operands are defined. This seems like a bad >> dependence to me, and that TableGen should match

On Thu, 04 Jun 2009 22:55:04 +0200, Pertti Kellomäki <pertti.kellomaki at tut.fi> wrote: > Hi Adam, > > John is right, the TCE stuff would be useful for you. Our > compiler targets a processor template that the designer can > populate pretty freely. The compiler then reads the architecture > description and creates an LLVM backend on the fly. > > Please don't

A simple question - using the following fishers test it appears that the P value is significant, but the CI includes 1. Is this result correct? > data.50p10min <- matrix(c(16,15, 8, 24),nrow=2) > fisher.test(data.50p10min) Fisher's Exact Test for Count Data data: data.50p10min p-value = 0.03941 alternative hypothesis: true odds ratio is not equal to 1 95