similar to: Codeowner for MIPS

Hi All, I'm going to be leaving Imagination on the 19th of August and moving on to a different LLVM opportunity at Apple a few weeks later. As such, I feel it's time for me to step down as code owner of the Mips target so that we have a single code owner throughout the LLVM 3.9 release which is scheduled to finish just after my last day. I'd like to nominate Simon Dardis as the new

On Tue, Aug 1, 2017 at 3:01 AM, Simon Dardis <Simon.Dardis at imgtec.com> wrote: > Currently I'm getting "Couldn't write to remote file "/home/testers/uploads/clang+llvm-5.0.0-rc1-mips-linux-gnu.tar.xz": Failure", > does that account need more space? Yes, the partition is full. I've asked Anton to see if we can fix this.

Thanks, that sounds like it would work. Was this based on what any other target did? Or do any other targets take this approach? I just want to make sure that we don't already have a hook suitable for this. Overriding runOnFunction to run what could be described as just a "late SelectionDAG pass" sounds pretty intrusive. Do you remember other approaches that didn't work? --

Hi, Looks ok for native MIPS, I have two failures on debian8: Failing Tests (2): XRay-x86_64-linux :: TestCases/Linux/argv0-log-file-name.cc XRay-x86_64-linux :: TestCases/Linux/fixedsize-logging.cc I'll investigate these failures. Otherwise looks ok. I've uploaded the binaries. 9d5a389c20eb5b3071e6a0504b7cf87d clang+llvm-4.0.0-rc1-mipsel-linux-gnu.tar.xz

Oh, one thing I forgot to mention: ReadOnly objects are also counted as small data globals on PPC (on top of BSS, Data, Common). That's what the r2 base is for (.sdata2, defined to be constant data). 32-bit immediate loads take 2 ops minimum on PPC, so even constant loading benefits from small data. It'd be handy to add a third argument containing what kind would normally be returned:

在 2017年04月26日 16:51, Simon Dardis 写道: > Hi Leslie, > > I've been seeing those failures as well (I own those buildbots). Like yourself, I'm a bit > uncertain as to why they're occurring. I'm currently investigating. I suspect it's a case > that the build directory has gone stale. Perhaps! and buildbots cover how many LLVM Backend targets? thanks! > >

Dear all, I am still a R apprentice... Apologies for the basic question. I am trying to reshape a dataframe based on the order of two variables (a character variable and a numerical variable). To simplify it, consider the following dataframe > df<-data.frame(id=c("b","b","a","a","a"),ord=c(2,1,1,3,2)) id ord 1 b 2 2 b 1 3 a 1 4

Hi all, I plan to deprecate the experimental microMIPS64R6 backend for the 5.0 release and remove it after the release. Currently there are no CPUs that use that particular sub-ISA which makes it difficult to justify the maintenance and parallel development effort. If there was a CPU design produced that did use microMIPS64R6, the backend could be restored from the archive. Any comments or

On Mon, 2016-04-18 at 09:18 -0700, Jeremy Allison wrote: > On Mon, Apr 18, 2016 at 03:39:02PM +0200, D Grealish wrote: > > Hi, > > I've been doing some research and testing into implementing SAMBA 4 > > as a > > AD/DC role for offering "AD as a service" to various small > > companies, I've > > been testing SAMBA out in various different

Just pinging this patch for review, particularly from PPC maintainers: https://reviews.llvm.org/D26344 It's now rebased for the latest master commits, `check-all` test results match those of the upstream base. There is also a clang driver patch, extending PPC target support for the `-G` flag: https://reviews.llvm.org/D26345 And lld patch implementing the _SDA_BASE_ symbols and includes an

Hi Simon, The page will be updated later today with the new rate. Kind regards, Arnaud On Tue, Feb 26, 2019 at 12:52 PM Simon Dardis via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > The EventBrite page is showing sales have ended, will it be reopening with > the higher rate soon? > > Thanks, > Simon > > On Tue, 26 Feb 2019 at 00:20, Tanya Lattner via

I've prepared a preliminary patch with the intention of implementing PPC-EABI subtarget features for applications that run in a standalone embedded environment. https://reviews.llvm.org/D26344 The most significant difference compared with the SVR4 ABI is the use of SDA (small data area). This allows full-word constants and data to be grouped into small-data sections accessed using relocated

Hi, No major issues seen so far for mips. Binaries uploaded. SHA256(clang+llvm-6.0.0-rc3-mipsel-linux-gnu.tar.xz)= 6e4fab79cc341a9084dab94cced108daff39fcde14a11e8d7ae454e9f92cb77c SHA256(clang+llvm-6.0.0-rc3-mips-linux-gnu.tar.xz)= 54887a039d3d7ccff17a0c7245f4c9d778a1c22f96b619db554849da55293d61 SHA256(clang+llvm-6.0.0-rc3-x86_64-linux-gnu-debian8.tar.xz)=

----- Original Message ----- > From: "Jack Andersen via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Wednesday, November 16, 2016 10:39:53 PM > Subject: Re: [llvm-dev] [MC] Target-Independent Small Data Section Handling > > Just pinging this patch for review, particularly from PPC > maintainers:

Hi Hans, I'm seeing one unexpected failure: libc++ :: std/input.output/stream.buffers/streambuf/streambuf.protected/streambuf.put.area/pbump2gig.pass.cpp Test logs show: Standard Error: -- terminating with uncaught exception of type std::length_error: basic_string -- but only on my big endian MIPS machine. I have filed PR36373 for the above failure. I've looked at the failures

Hi, I'm seeming new regressions form 4.0.0 for mips big endian: DataFlowSanitizer-mips64 :: custom.cc DataFlowSanitizer-mips64 :: propagate.c SanitizerCommon-asan-mips-Linux :: sanitizer_coverage_trace_pc_guard-dso.cc SanitizerCommon-asan-mips-Linux :: sanitizer_coverage_trace_pc_guard.cc SanitizerCommon-asan-mips64-Linux :: Linux/getpwnam_r_invalid_user.cc

hi, im so sorry i made you confuse, lets make things simple, i will attach here my config file (the passwords are the default for now). and see if this configuration will now work over the internet and can be heard publicly, I only change the hostname, also please check it if it's the correct one. thanks for your kind consideration. On Fri, Mar 29, 2019 at 2:06 PM Thomas B. Rücker

Hi Leslie, On 20 December 2017 at 10:51, Leslie Zhai via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Sorry, I am apprentice of lowRISC, and meet new bug when porting GlobalISel > to RISCV target > https://github.com/xiangzhai/llvm/commit/b3f91ea54d9fee0ef7e73a32c6b8456bbe252811 > > > In file included from >

It wouldn't take me more than an hour or two to do the format conversion. It is rather trivial, actually. Just say the word and I'm on to it like a starving bee. I guess I should get used to using the Sphinx layout; I'm simply more familiar with the format I use on my own websites. Have you guys ever considered making a less formal wiki for LLVM documentation - a place where tiny

I looked around the codebase and didn't see anything that obviously looked like the natural place to turn constant zero immediates into zero-registers (i.e. registers that always return zero when read). Right now we are expanding them in ISelLowering::LowerOperation but that seems too early. The specific issue I'm hitting is that we have a register that reads as -1 and so when we replace