similar to: i686-mingw32-RA-on-linux buildbot

Hello, I was curious if there was any advice on how to get a code-review restarted/completed. The two I've submitted recently (D30107<https://reviews.llvm.org/D30107> D29923<https://reviews.llvm.org/D29923>) have gotten a bit of review but both then seem to stall. Any hints? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL:

Ughs, I'm not dying to wait months...but if it thats the way it is, then its the way it is. Tends to be so many commits in a day it seemed it was being lost in the noise/clique. I did try to add some notes to the bug tracker, but new logins are disabled, and the email to get one never replied...but I guess that's another topic! Thanks again, definitely alleviated some frustrations.

Thanks. I have gone that route and there was no response. What constitutes 'particularly urgent'? In regards to D30107<https://reviews.llvm.org/D30107> it some fairly obvious defect(s) and there are a few bugs open in your database about the issue, but it seems an area that doesn't get much interest (related to DynamicLibrary class). Thanks again.

I ran into a similar problem a while ago; see https://reviews.llvm.org/D30107 and https://reviews.llvm.org/D33515 .  You get the unusual stack trace because it's trying to call a destructor in shared library which was already unloaded. I thought we had fixed that, but maybe not?  Looking again, it looks like the patch got reverted and I didn't notice. -Eli On 5/14/2018 10:18 PM,

It's working with trunk though. Do you think the patch will end up in 6.0.1? Thanks. Simone On Tue, May 15, 2018 at 11:18 AM, Friedman, Eli <efriedma at codeaurora.org> wrote: > I ran into a similar problem a while ago; see https://reviews.llvm.org/ > D30107 and https://reviews.llvm.org/D33515 . You get the unusual stack > trace because it's trying to call a destructor

This is the correct path to the pass: https://github.com/PRUNERS/sword/blob/master/lib/Transforms/Instrumentation/InstrumentParallel.cpp On Mon, May 14, 2018 at 10:06 PM, Simone Atzeni <simone.at at gmail.com> wrote: > Hi all, > > I was porting my pass from LLVM 4.0 to 6.0 and I am getting a segmentation > fault. > I was able to obtain only the info below from GDB. > >

Hello, I am just curious...which is faster? Obviously if the machines are the same size and all conditions are equal except for the OS. Regards, Jake Johnson jake@plutoid.com ______________________________________________________________________ Plutoid - http://www.plutoid.com - Shop Plutoid for the best prices on Rims, Car Audio, and Performance Parts.

Hi all, I was porting my pass from LLVM 4.0 to 6.0 and I am getting a segmentation fault. I was able to obtain only the info below from GDB. I tried to debug with some printf and the runOnFunction runs correctly. Any idea/suggestion about what is going on? The source code of the pass is here: https://github.com/PRUNERS/sword/blob/master/lib/Sword.cpp Any help is much appreciated, Thanks!

Hi everyone, It took me a while to figure this out properly, as I kept getting circular or missing dependencies with video drivers. This set of three patches should simplify the situation a bit, mostly by cleaning up the dependencies around CONFIG_ACPI_VIDEO. With all three patches applied, I no longer run into those related warnings. If everyone agrees on the general direction, I hope we can

Hi. I've found inconstancy between output of repoquery and rpm. I was looking forward towards apache php 5.4 module which must provided by some package SCL (can someone tell me?). rpm -qf /etc/httpd/modules/mod_proxy.so httpd-2.2.15-29.el6.centos.x86_64 repoquery -qf /etc/httpd/modules/mod_proxy.so so repoquery results in no output yum list installed httpd Loaded plugins: fastestmirror

https://bugzilla.netfilter.org/bugzilla/show_bug.cgi?id=505 kaber@trash.net changed: What |Removed |Added ---------------------------------------------------------------------------- AssignedTo|laforge@netfilter.org |pablo@netfilter.org Version|CVS (please indicate |1.1.2 ------- Additional Comments From kaber@trash.net

Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you will have to compile with -O3. You can also invoke the MI (pre-RA) scheduler with llc option "-enable-misched". As you have pointed out, the post-isel scheduler is mandatory, and therefore you don't have to give any command line options. Currently, mips has only one generic scheduling itinerary model in

Hi, LLVM, I found LLVM codegen has 3 passes for instruction scheduling: 1) pre-ra sched 2) post-ra sched 3) mi sched. for RISC machines, there are data hazard cases appear only after Register Allocation(RA). for example, $t0 is used immediately after writing(RAW): ld $t0, MEM add $t2, $t0, $0 There may be one or more stall in pipeline. Instruction scheduler can detect this kinds of conflict

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Akira, > > I found you maintain mips MipsSchedule.td. does it correct? in > MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no > ByPass info out there. > are you sure this reflects the real R4xxx/R5xxx processors. > > why IILoad uses funcition unit ALU? >

Sorry for the off topic. When I login my Phabricator account, I see there is alarm saying "Account Setup Issue: Primary Email Unverified". I cannot see where to ask Phabricator send verification mail to my primary email address. Could you help me out? :-) Thanks. Regards, chenwj 2017-04-24 18:35 GMT+08:00 Eric Liu via cfe-dev <cfe-dev at lists.llvm.org>: > It's working

Hi, Akira, I found you maintain mips MipsSchedule.td. does it correct? in MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no ByPass info out there. are you sure this reflects the real R4xxx/R5xxx processors. why IILoad uses funcition unit ALU? InstrItinData<IILoad , [InstrStage<3, [ALU]>]> for my previous question, I have new input after

Dear People, I have following situation with "OpenSSH_3.6.1p2, SSH protocols 1.5/2.0, OpenSSL 0x0090701f": a) I will send files via scp to: "OpenSSH_3.8p1, SSH protocols 1.5/2.0, OpenSSL 0.9.7d 17 Mar 2004" b) used command: scp [-vvv] -p -B -C /home/gdg/generation/cr/test_lnx50/lnx50.test2.000001 gdg at lnx50:/home/gdg/EMPFANG/lnx50.test2 Login without PW runs fine,

Akira, Thanks you for response. I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But I found mips codes are good enough by default. basically, I can not easily eyeball any bubbles. I don't understand how they can do that without post-RA-sched. pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little information and they can only schedule node in topology

Hi Christoph, bin/shader_runner tests/spec/glsl-1.40/uniform_buffer/fs-struct-copy-complicated.shader_test -auto bin/shader_runner tests/spec/glsl-1.40/uniform_buffer/vs-struct-copy-complicated.shader_test -auto bin/shader_runner tests/spec/glsl-1.50/uniform_buffer/gs-struct-copy-complicated.shader_test -auto Now all segfault. I reverted 2e9ee44797 ("nv50/ir/ra: some register spilling

Dear LLVM community, In 2007 Lang Hames developed a Graph Coloring Register Allocator. This allocator was created based on the paper " A generalized algorithm for graph-coloring register allocation" (http://doi.acm.org/10.1145/996841.996875). This algorithm is graph based, and is concerned with register banks that have different register classes and registers that alias. Lang